Commit 3fade948 authored by Vinod Koul's avatar Vinod Koul Committed by Stephen Boyd
Browse files

clk: qcom: gcc-sm8350: add gdsc 



Add the GDSC found in GCC for SM8350 SoC

Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210210161649.431741-1-vkoul@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent e16831bf

drivers/clk/qcom/gcc-sm8350.c

+100 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include "clk-regmap.h"

#include "clk-regmap-divider.h"

#include "clk-regmap-mux.h"

#include "gdsc.h"

#include "reset.h"



enum {
@@ -3452,6 +3453,90 @@ static struct clk_branch gcc_video_axi1_clk = { 
	},

};



static struct gdsc pcie_0_gdsc = {

	.gdscr = 0x6b004,

	.pd = {

		.name = "pcie_0_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct gdsc pcie_1_gdsc = {

	.gdscr = 0x8d004,

	.pd = {

		.name = "pcie_1_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct gdsc ufs_card_gdsc = {

	.gdscr = 0x75004,

	.pd = {

		.name = "ufs_card_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct gdsc ufs_phy_gdsc = {

	.gdscr = 0x77004,

	.pd = {

		.name = "ufs_phy_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct gdsc usb30_prim_gdsc = {

	.gdscr = 0xf004,

	.pd = {

		.name = "usb30_prim_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct gdsc usb30_sec_gdsc = {

	.gdscr = 0x10004,

	.pd = {

		.name = "usb30_sec_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

};



static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {

	.gdscr = 0x7d050,

	.pd = {

		.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = VOTABLE,

};



static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {

	.gdscr = 0x7d058,

	.pd = {

		.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = VOTABLE,

};



static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {

	.gdscr = 0x7d054,

	.pd = {

		.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = VOTABLE,

};



static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {

	.gdscr = 0x7d06c,

	.pd = {

		.name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = VOTABLE,

};



static struct clk_regmap *gcc_sm8350_clocks[] = {

	[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,

	[GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
@@ -3646,6 +3731,19 @@ static struct clk_regmap *gcc_sm8350_clocks[] = { 
	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,

};



static struct gdsc *gcc_sm8350_gdscs[] = {

	[PCIE_0_GDSC] = &pcie_0_gdsc,

	[PCIE_1_GDSC] = &pcie_1_gdsc,

	[UFS_CARD_GDSC] = &ufs_card_gdsc,

	[UFS_PHY_GDSC] = &ufs_phy_gdsc,

	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,

	[USB30_SEC_GDSC] = &usb30_sec_gdsc,

	[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,

	[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,

	[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,

	[HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,

};



static const struct qcom_reset_map gcc_sm8350_resets[] = {

	[GCC_CAMERA_BCR] = { 0x26000 },

	[GCC_DISPLAY_BCR] = { 0x27000 },
@@ -3724,6 +3822,8 @@ static const struct qcom_cc_desc gcc_sm8350_desc = { 
	.num_clks = ARRAY_SIZE(gcc_sm8350_clocks),

	.resets = gcc_sm8350_resets,

	.num_resets = ARRAY_SIZE(gcc_sm8350_resets),

	.gdscs = gcc_sm8350_gdscs,

	.num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),

};



static const struct of_device_id gcc_sm8350_match_table[] = {

include/dt-bindings/clock/qcom,gcc-sm8350.h

+12 −0
Original line number Diff line number Diff line
@@ -251,4 +251,16 @@ 
#define GCC_VIDEO_AXI1_CLK_ARES					36

#define GCC_VIDEO_BCR						37



/* GCC power domains */

#define PCIE_0_GDSC						0

#define PCIE_1_GDSC						1

#define UFS_CARD_GDSC						2

#define UFS_PHY_GDSC						3

#define USB30_PRIM_GDSC						4

#define USB30_SEC_GDSC						5

#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC			6

#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC			7

#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC			8

#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC			9



#endif