Commit 3f86ed6e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC updates from Vineet Gupta:

 - fixes for -Wmissing-prototype warnings

 - missing compiler barrier in relaxed atomics

 - some uaccess simplification, declutter

 - removal of massive glocal struct cpuinfo_arc from bootlog code

 - __switch_to consolidation (removal of inline asm variant)

 - use GP to cache task pointer (vs. r25)

 - misc rework of entry code

* tag 'arc-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (24 commits)
  ARC: boot log: fix warning
  arc: Explicitly include correct DT includes
  ARC: pt_regs: create seperate type for ecr
  ARCv2: entry: rearrange pt_regs slightly
  ARC: entry: replace 8 byte ADD.ne with 4 byte ADD2.ne
  ARC: entry: replace 8 byte OR with 4 byte BSET
  ARC: entry: Add more common chores to EXCEPTION_PROLOGUE
  ARC: entry: EV_MachineCheck dont re-read ECR
  ARC: entry: ARcompact EV_ProtV to use r10 directly
  ARC: entry: rework (non-functional)
  ARC: __switch_to: move ksp to thread_info from thread_struct
  ARC: __switch_to: asm with dwarf ops (vs. inline asm)
  ARC: kernel stack: INIT_THREAD need not setup @init_stack in @ksp
  ARC: entry: use gp to cache task pointer (vs. r25)
  ARC: boot log: eliminate struct cpuinfo_arc #4: boot log per ISA
  ARC: boot log: eliminate struct cpuinfo_arc #3: don't export
  ARC: boot log: eliminate struct cpuinfo_arc #2: cache
  ARC: boot log: eliminate struct cpuinfo_arc #1: mm
  ARCv2: memset: don't prefetch for len == 0 which happens a alot
  ARC: uaccess: elide unaliged handling if hardware supports
  ...
parents ea4f9c37 c40cad3b

arch/arc/Kconfig

+5 −3
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ config ARC 
	select GENERIC_SCHED_CLOCK

	select GENERIC_SMP_IDLE_THREAD

	select GENERIC_IOREMAP

	select GENERIC_STRNCPY_FROM_USER if MMU

	select GENERIC_STRNLEN_USER if MMU

	select HAVE_ARCH_KGDB

	select HAVE_ARCH_TRACEHOOK

	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
@@ -491,11 +493,11 @@ config ARC_KVADDR_SIZE 
	  kernel-user gutter)



config ARC_CURR_IN_REG

	bool "Dedicate Register r25 for current_task pointer"

	bool "cache current task pointer in gp"

	default y

	help

	  This reserved Register R25 to point to Current Task in

	  kernel mode. This saves memory access for each such access

	  This reserves gp register to point to Current Task in

	  kernel mode eliding memory access for each access





config ARC_EMUL_UNALIGNED

arch/arc/Makefile

+3 −3
Original line number Diff line number Diff line
@@ -28,14 +28,14 @@ cflags-y += $(tune-mcpu-def-y) 
endif

endif





ifdef CONFIG_ARC_CURR_IN_REG

# For a global register definition, make sure it gets passed to every file

# We had a customer reported bug where some code built in kernel was NOT using

# any kernel headers, and missing the r25 global register

# any kernel headers, and missing the global register

# Can't do unconditionally because of recursive include issues

# due to <linux/thread_info.h>

LINUXINCLUDE	+=  -include $(srctree)/arch/arc/include/asm/current.h

cflags-y	+= -ffixed-gp

endif



cflags-y				+= -fsection-anchors
@@ -67,7 +67,7 @@ cflags-$(CONFIG_ARC_DW2_UNWIND) += -fasynchronous-unwind-tables $(cfi) 
# small data is default for elf32 tool-chain. If not usable, disable it

# This also allows repurposing GP as scratch reg to gcc reg allocator

disable_small_data := y

cflags-$(disable_small_data)		+= -mno-sdata -fcall-used-gp

cflags-$(disable_small_data)		+= -mno-sdata



cflags-$(CONFIG_CPU_BIG_ENDIAN)		+= -mbig-endian

ldflags-$(CONFIG_CPU_BIG_ENDIAN)	+= -EB

arch/arc/include/asm/arcregs.h

+55 −44
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
#define ARC_REG_ICCM_BUILD	0x78	/* ICCM size (common) */

#define ARC_REG_XY_MEM_BCR	0x79

#define ARC_REG_MAC_BCR		0x7a

#define ARC_REG_MUL_BCR		0x7b

#define ARC_REG_MPY_BCR		0x7b

#define ARC_REG_SWAP_BCR	0x7c

#define ARC_REG_NORM_BCR	0x7d

#define ARC_REG_MIXMAX_BCR	0x7e
@@ -177,7 +177,7 @@ struct bcr_isa_arcv2 { 
#endif

};



struct bcr_uarch_build_arcv2 {

struct bcr_uarch_build {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int pad:8, prod:8, maj:8, min:8;

#else
@@ -185,6 +185,59 @@ struct bcr_uarch_build_arcv2 { 
#endif

};



struct bcr_mmu_3 {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,

		     u_itlb:4, u_dtlb:4;

#else

	unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,

		     ways:4, ver:8;

#endif

};



struct bcr_mmu_4 {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,

		     n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;

#else

	/*           DTLB      ITLB      JES        JE         JA      */

	unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,

		     pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;

#endif

};



struct bcr_cache {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;

#else

	unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;

#endif

};



struct bcr_slc_cfg {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int pad:24, way:2, lsz:2, sz:4;

#else

	unsigned int sz:4, lsz:2, way:2, pad:24;

#endif

};



struct bcr_clust_cfg {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;

#else

	unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;

#endif

};



struct bcr_volatile {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int start:4, limit:4, pad:22, order:1, disable:1;

#else

	unsigned int disable:1, order:1, pad:22, limit:4, start:4;

#endif

};



struct bcr_mpy {

#ifdef CONFIG_CPU_BIG_ENDIAN

	unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
@@ -302,48 +355,6 @@ struct bcr_generic { 
#endif

};



/*

 *******************************************************************

 * Generic structures to hold build configuration used at runtime

 */



struct cpuinfo_arc_mmu {

	unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;

	unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;

};



struct cpuinfo_arc_cache {

	unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;

};



struct cpuinfo_arc_bpu {

	unsigned int ver, full, num_cache, num_pred, ret_stk;

};



struct cpuinfo_arc_ccm {

	unsigned int base_addr, sz;

};



struct cpuinfo_arc {

	struct cpuinfo_arc_cache icache, dcache, slc;

	struct cpuinfo_arc_mmu mmu;

	struct cpuinfo_arc_bpu bpu;

	struct bcr_identity core;

	struct bcr_isa_arcv2 isa;

	const char *release, *name;

	unsigned int vec_base;

	struct cpuinfo_arc_ccm iccm, dccm;

	struct {

		unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,

			     fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,

			     ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,

			     timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;

	} extn;

	struct bcr_mpy extn_mpy;

};



extern struct cpuinfo_arc cpuinfo_arc700[];



static inline int is_isa_arcv2(void)

{

	return IS_ENABLED(CONFIG_ISA_ARCV2);

arch/arc/include/asm/atomic-llsc.h

+3 −3
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ static inline void arch_atomic_##op(int i, atomic_t *v) \ 
	: [val]	"=&r"	(val) /* Early clobber to prevent reg reuse */	\

	: [ctr]	"r"	(&v->counter), /* Not "m": llock only supports reg direct addr mode */	\

	  [i]	"ir"	(i)						\

	: "cc");							\

	: "cc", "memory");						\

}									\



#define ATOMIC_OP_RETURN(op, asm_op)				\
@@ -34,7 +34,7 @@ static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \ 
	: [val]	"=&r"	(val)						\

	: [ctr]	"r"	(&v->counter),					\

	  [i]	"ir"	(i)						\

	: "cc");							\

	: "cc", "memory");						\

									\

	return val;							\

}
@@ -56,7 +56,7 @@ static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \ 
	  [orig] "=&r" (orig)						\

	: [ctr]	"r"	(&v->counter),					\

	  [i]	"ir"	(i)						\

	: "cc");							\

	: "cc", "memory");						\

									\

	return orig;							\

}

arch/arc/include/asm/atomic64-arcv2.h

+3 −3
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ static inline void arch_atomic64_##op(s64 a, atomic64_t *v) \ 
	"	bnz     1b		\n"				\

	: "=&r"(val)							\

	: "r"(&v->counter), "ir"(a)					\

	: "cc");							\

	: "cc", "memory");						\

}									\



#define ATOMIC64_OP_RETURN(op, op1, op2)		        	\
@@ -77,7 +77,7 @@ static inline s64 arch_atomic64_##op##_return_relaxed(s64 a, atomic64_t *v) \ 
	"	bnz     1b		\n"				\

	: [val] "=&r"(val)						\

	: "r"(&v->counter), "ir"(a)					\

	: "cc");	/* memory clobber comes from smp_mb() */	\

	: "cc", "memory");						\

									\

	return val;							\

}
@@ -99,7 +99,7 @@ static inline s64 arch_atomic64_fetch_##op##_relaxed(s64 a, atomic64_t *v) \ 
	"	bnz     1b		\n"				\

	: "=&r"(orig), "=&r"(val)					\

	: "r"(&v->counter), "ir"(a)					\

	: "cc");	/* memory clobber comes from smp_mb() */	\

	: "cc", "memory");						\

									\

	return orig;							\

}