Commit 3f68c01b authored by Zhan Liu's avatar Zhan Liu Committed by Alex Deucher
Browse files

drm/amd/display: add cyan_skillfish display support



[Why]
add display related cyan_skillfish files in.

makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.

v2: squash in clang fixes from Harry, Nathan
v3: squash in missing CONFIG_DRM_AMD_DC check (Alex)

Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Signed-off-by: default avatarZhan Liu <zhan.liu@amd.com>
Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0ad53fe3
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+1 −0
Original line number Diff line number Diff line
@@ -3241,6 +3241,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
	case CHIP_NAVI14:
	case CHIP_NAVI12:
	case CHIP_RENOIR:
	case CHIP_CYAN_SKILLFISH:
	case CHIP_SIENNA_CICHLID:
	case CHIP_NAVY_FLOUNDER:
	case CHIP_DIMGREY_CAVEFISH:
+4 −0
Original line number Diff line number Diff line
@@ -906,6 +906,10 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
		}
		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
		else if (amdgpu_device_has_dc_support(adev))
			amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif
		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
		break;
+9 −0
Original line number Diff line number Diff line
@@ -17,6 +17,15 @@ config DRM_AMD_DC_DCN
	help
	  Raven, Navi, and newer family support for display engine

config DRM_AMD_DC_DCN201
	bool "Enable DCN201 support in DC"
	default y
	depends on DRM_AMD_DC && X86
	depends on DRM_AMD_DC_DCN
	help
	  Choose this option if you want to have
	  201 support for display engine

config DRM_AMD_DC_HDCP
	bool "Enable HDCP support in DC"
	depends on DRM_AMD_DC
+10 −0
Original line number Diff line number Diff line
@@ -1352,6 +1352,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
	case CHIP_YELLOW_CARP:
		init_data.flags.gpu_vm_support = true;
		break;
	case CHIP_CYAN_SKILLFISH:
		init_data.flags.disable_dmcu = true;
		break;
	default:
		break;
	}
@@ -1647,6 +1650,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
	case CHIP_BEIGE_GOBY:
	case CHIP_VANGOGH:
	case CHIP_YELLOW_CARP:
	case CHIP_CYAN_SKILLFISH:
		return 0;
	case CHIP_NAVI12:
		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -4182,6 +4186,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
	case CHIP_DIMGREY_CAVEFISH:
	case CHIP_BEIGE_GOBY:
	case CHIP_VANGOGH:
	case CHIP_CYAN_SKILLFISH:
	case CHIP_YELLOW_CARP:
		if (dcn10_register_irq_handlers(dm->adev)) {
			DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -4359,6 +4364,11 @@ static int dm_early_init(void *handle)
		adev->mode_info.num_hpd = 4;
		adev->mode_info.num_dig = 4;
		break;
	case CHIP_CYAN_SKILLFISH:
		adev->mode_info.num_crtc = 2;
		adev->mode_info.num_hpd = 2;
		adev->mode_info.num_dig = 2;
		break;
	case CHIP_NAVI14:
	case CHIP_DIMGREY_CAVEFISH:
		adev->mode_info.num_crtc = 5;
+3 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ DC_LIBS += dcn20
DC_LIBS += dsc
DC_LIBS += dcn10 dml
DC_LIBS += dcn21
ifdef CONFIG_DRM_AMD_DC_DCN201
DC_LIBS += dcn201
endif
DC_LIBS += dcn30
DC_LIBS += dcn301
DC_LIBS += dcn302
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