Commit 3f66bf40 authored by Nirmoy Das's avatar Nirmoy Das Committed by Alex Deucher
Browse files

drm/amdgpu: fix compute queue priority if num_kcq is less than 4 



Compute queues are configurable with module param, num_kcq.
amdgpu_gfx_is_high_priority_compute_queue was setting 1st 4 queues to
high priority queue leaving a null drm scheduler in
adev->gpu_sched[hw_ip]["normal_prio"].sched if num_kcq < 5.

This patch tries to fix it by alternating compute queue priority between
normal and high priority.

Fixes: 33abcb1f (drm/amdgpu: set compute queue priority at mqd_init)
Signed-off-by: default avatarNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3617e579

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+7 −3
Original line number Diff line number Diff line
@@ -193,10 +193,14 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) 
}



bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,

					       int queue)

					       int pipe, int queue)

{

	/* Policy: make queue 0 of each pipe as high priority compute queue */

	return (queue == 0);

	bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);

	int cond;

	/* Policy: alternate between normal and high priority */

	cond = multipipe_policy ? pipe : queue;



	return ((cond % 2) != 0);



}

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+1 −1
Original line number Diff line number Diff line
@@ -374,7 +374,7 @@ void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,

				     int pipe, int queue);

bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,

					       int queue);

					       int pipe, int queue);

int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,

			       int pipe, int queue);

void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −2
Original line number Diff line number Diff line
@@ -4473,7 +4473,8 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 
	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP

		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)

		+ ring->pipe;

	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?

	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,

							    ring->queue) ?

			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;

	/* type-2 packets are deprecated on MEC, use type-3 instead */

	r = amdgpu_ring_init(adev, ring, 1024,
@@ -6508,7 +6509,8 @@ static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct 
	struct amdgpu_device *adev = ring->adev;



	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {

		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,

							      ring->queue)) {

			mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;

			mqd->cp_hqd_queue_priority =

				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+4 −2
Original line number Diff line number Diff line
@@ -1923,7 +1923,8 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 
		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)

		+ ring->pipe;



	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?

	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,

							    ring->queue) ?

			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;

	/* type-2 packets are deprecated on MEC, use type-3 instead */

	r = amdgpu_ring_init(adev, ring, 1024,
@@ -4441,7 +4442,8 @@ static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *m 
	struct amdgpu_device *adev = ring->adev;



	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {

		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,

							      ring->queue)) {

			mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;

			mqd->cp_hqd_queue_priority =

				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+5 −2
Original line number Diff line number Diff line
@@ -2228,7 +2228,8 @@ static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 
	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP

		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)

		+ ring->pipe;

	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?

	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,

							    ring->queue) ?

			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;

	/* type-2 packets are deprecated on MEC, use type-3 instead */

	return amdgpu_ring_init(adev, ring, 1024,
@@ -3383,7 +3384,9 @@ static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *m 
	struct amdgpu_device *adev = ring->adev;



	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {

		if (amdgpu_gfx_is_high_priority_compute_queue(adev,

							      ring->pipe,

							      ring->queue)) {

			mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;

			mqd->cp_hqd_queue_priority =

				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;