Commit 3f654e14 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/dg2: Add Wa_22014226127 



New DG2 workaround added to specification.

BSpec: 54077
BSpec: 66622
BSpec: 54833
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220325142249.81443-1-jose.souza@intel.com
parent 552caa1f

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -1088,6 +1088,7 @@ 
#define EU_PERF_CNTL3				_MMIO(0xe758)



#define LSC_CHICKEN_BIT_0			_MMIO(0xe7c8)

#define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)

#define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT	REG_BIT(15)

#define LSC_CHICKEN_BIT_0_UDW			_MMIO(0xe7c8 + 4)

#define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+5 −0
Original line number Diff line number Diff line
@@ -2624,6 +2624,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 
		wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |

				GLOBAL_INVALIDATION_MODE);

	}



	if (IS_DG2(i915)) {

		/* Wa_22014226127:dg2 */

		wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);

	}

}



static void