Commit 3f2bc385 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a5xx: Disable UCHE global filter 



Port over the command from downstream to prevent undefined
behaviour.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent cce212d8

drivers/gpu/drm/msm/adreno/a5xx.xml.h

+2 −0
Original line number Diff line number Diff line
@@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) 


#define REG_A5XX_UCHE_ADDR_MODE_CNTL				0x00000e80



#define REG_A5XX_UCHE_MODE_CNTL					0x00000e81



#define REG_A5XX_UCHE_SVM_CNTL					0x00000e82



#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO			0x00000e87

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+3 −0
Original line number Diff line number Diff line
@@ -754,6 +754,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	    adreno_is_a512(adreno_gpu))

		gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));



	/* Disable UCHE global filter as SP can invalidate/flush independently */

	gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29));



	/* Enable USE_RETENTION_FLOPS */

	gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);