Commit 3f1c24b9 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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clk: qcom: gcc-msm8939: switch to parent_hws 



Change several entries of parent_data to use parent_hws instead, which
results in slightly more ovbious code.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103145515.1164020-7-dmitry.baryshkov@linaro.org
parent a2a796c1

drivers/clk/qcom/gcc-msm8939.c

+16 −16
Original line number Diff line number Diff line
@@ -73,8 +73,8 @@ static struct clk_regmap gpll0_vote = { 
	.enable_mask = BIT(0),

	.hw.init = &(struct clk_init_data){

		.name = "gpll0_vote",

		.parent_data = &(const struct clk_parent_data) {

			.hw = &gpll0.clkr.hw,

		.parent_hws = (const struct clk_hw*[]) {

			&gpll0.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,
@@ -104,8 +104,8 @@ static struct clk_regmap gpll1_vote = { 
	.enable_mask = BIT(1),

	.hw.init = &(struct clk_init_data){

		.name = "gpll1_vote",

		.parent_data = &(const struct clk_parent_data) {

			.hw = &gpll1.clkr.hw,

		.parent_hws = (const struct clk_hw*[]) {

			&gpll1.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,
@@ -135,8 +135,8 @@ static struct clk_regmap gpll2_vote = { 
	.enable_mask = BIT(2),

	.hw.init = &(struct clk_init_data){

		.name = "gpll2_vote",

		.parent_data = &(const struct clk_parent_data) {

			.hw = &gpll2.clkr.hw,

		.parent_hws = (const struct clk_hw*[]) {

			&gpll2.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,
@@ -166,8 +166,8 @@ static struct clk_regmap bimc_pll_vote = { 
	.enable_mask = BIT(3),

	.hw.init = &(struct clk_init_data){

		.name = "bimc_pll_vote",

		.parent_data = &(const struct clk_parent_data) {

			.hw = &bimc_pll.clkr.hw,

		.parent_hws = (const struct clk_hw*[]) {

			&bimc_pll.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,
@@ -197,8 +197,8 @@ static struct clk_regmap gpll3_vote = { 
	.enable_mask = BIT(4),

	.hw.init = &(struct clk_init_data){

		.name = "gpll3_vote",

		.parent_data = &(const struct clk_parent_data) {

			.hw = &gpll3.clkr.hw,

		.parent_hws = (const struct clk_hw*[]) {

			&gpll3.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,
@@ -244,8 +244,8 @@ static struct clk_regmap gpll4_vote = { 
	.enable_mask = BIT(5),

	.hw.init = &(struct clk_init_data){

		.name = "gpll4_vote",

		.parent_data = &(const struct clk_parent_data) {

			.hw = &gpll4.clkr.hw,

		.parent_hws = (const struct clk_hw*[]) {

			&gpll4.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,
@@ -290,8 +290,8 @@ static struct clk_regmap gpll5_vote = { 
	.enable_mask = BIT(6),

	.hw.init = &(struct clk_init_data){

		.name = "gpll5_vote",

		.parent_data = &(const struct clk_parent_data) {

			.hw = &gpll5.clkr.hw,

		.parent_hws = (const struct clk_hw*[]) {

			&gpll5.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,
@@ -321,8 +321,8 @@ static struct clk_regmap gpll6_vote = { 
	.enable_mask = BIT(7),

	.hw.init = &(struct clk_init_data){

		.name = "gpll6_vote",

		.parent_data = &(const struct clk_parent_data) {

			.hw = &gpll6.clkr.hw,

		.parent_hws = (const struct clk_hw*[]) {

			&gpll6.clkr.hw,

		},

		.num_parents = 1,

		.ops = &clk_pll_vote_ops,