Commit 3ef3ace4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cpu_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpu updates from Borislav Petkov:

 - Split MTRR and PAT init code to accomodate at least Xen PV and TDX
   guests which do not get MTRRs exposed but only PAT. (TDX guests do
   not support the cache disabling dance when setting up MTRRs so they
   fall under the same category)

   This is a cleanup work to remove all the ugly workarounds for such
   guests and init things separately (Juergen Gross)

 - Add two new Intel CPUs to the list of CPUs with "normal" Energy
   Performance Bias, leading to power savings

 - Do not do bus master arbitration in C3 (ARB_DISABLE) on modern
   Centaur CPUs

* tag 'x86_cpu_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits)
  x86/mtrr: Make message for disabled MTRRs more descriptive
  x86/pat: Handle TDX guest PAT initialization
  x86/cpuid: Carve out all CPUID functionality
  x86/cpu: Switch to cpu_feature_enabled() for X86_FEATURE_XENPV
  x86/cpu: Remove X86_FEATURE_XENPV usage in setup_cpu_entry_area()
  x86/cpu: Drop 32-bit Xen PV guest code in update_task_stack()
  x86/cpu: Remove unneeded 64-bit dependency in arch_enter_from_user_mode()
  x86/cpufeatures: Add X86_FEATURE_XENPV to disabled-features.h
  x86/acpi/cstate: Optimize ARB_DISABLE on Centaur CPUs
  x86/mtrr: Simplify mtrr_ops initialization
  x86/cacheinfo: Switch cache_ap_init() to hotplug callback
  x86: Decouple PAT and MTRR handling
  x86/mtrr: Add a stop_machine() handler calling only cache_cpu_init()
  x86/mtrr: Let cache_aps_delayed_init replace mtrr_aps_delayed_init
  x86/mtrr: Get rid of __mtrr_enabled bool
  x86/mtrr: Simplify mtrr_bp_init()
  x86/mtrr: Remove set_all callback from struct mtrr_ops
  x86/mtrr: Disentangle MTRR init from PAT init
  x86/mtrr: Move cache control code to cacheinfo.c
  x86/mtrr: Split MTRR-specific handling from cache dis/enabling
  ...
parents 4eb77fa1 7882b69e

arch/x86/include/asm/cacheinfo.h

+13 −0
Original line number Diff line number Diff line
@@ -2,7 +2,20 @@ 
#ifndef _ASM_X86_CACHEINFO_H

#define _ASM_X86_CACHEINFO_H



/* Kernel controls MTRR and/or PAT MSRs. */

extern unsigned int memory_caching_control;

#define CACHE_MTRR 0x01

#define CACHE_PAT  0x02



void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu);

void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu);



void cache_disable(void);

void cache_enable(void);

void set_cache_aps_delayed_init(bool val);

bool get_cache_aps_delayed_init(void);

void cache_bp_init(void);

void cache_bp_restore(void);

void cache_aps_init(void);



#endif /* _ASM_X86_CACHEINFO_H */

arch/x86/include/asm/cpuid.h

+139 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * CPUID-related helpers/definitions

 *

 * Derived from arch/x86/kvm/cpuid.c

 */



#ifndef _ASM_X86_CPUID_H

#define _ASM_X86_CPUID_H



#include <asm/string.h>



struct cpuid_regs {

	u32 eax, ebx, ecx, edx;

};



enum cpuid_regs_idx {

	CPUID_EAX = 0,

	CPUID_EBX,

	CPUID_ECX,

	CPUID_EDX,

};



#ifdef CONFIG_X86_32

extern int have_cpuid_p(void);

#else

static inline int have_cpuid_p(void)

{

	return 1;

}

#endif

static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,

				unsigned int *ecx, unsigned int *edx)

{

	/* ecx is often an input as well as an output. */

	asm volatile("cpuid"

	    : "=a" (*eax),

	      "=b" (*ebx),

	      "=c" (*ecx),

	      "=d" (*edx)

	    : "0" (*eax), "2" (*ecx)

	    : "memory");

}



#define native_cpuid_reg(reg)					\

static inline unsigned int native_cpuid_##reg(unsigned int op)	\

{								\

	unsigned int eax = op, ebx, ecx = 0, edx;		\

								\

	native_cpuid(&eax, &ebx, &ecx, &edx);			\

								\

	return reg;						\

}



/*

 * Native CPUID functions returning a single datum.

 */

native_cpuid_reg(eax)

native_cpuid_reg(ebx)

native_cpuid_reg(ecx)

native_cpuid_reg(edx)



#ifdef CONFIG_PARAVIRT_XXL

#include <asm/paravirt.h>

#else

#define __cpuid			native_cpuid

#endif



/*

 * Generic CPUID function

 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx

 * resulting in stale register contents being returned.

 */

static inline void cpuid(unsigned int op,

			 unsigned int *eax, unsigned int *ebx,

			 unsigned int *ecx, unsigned int *edx)

{

	*eax = op;

	*ecx = 0;

	__cpuid(eax, ebx, ecx, edx);

}



/* Some CPUID calls want 'count' to be placed in ecx */

static inline void cpuid_count(unsigned int op, int count,

			       unsigned int *eax, unsigned int *ebx,

			       unsigned int *ecx, unsigned int *edx)

{

	*eax = op;

	*ecx = count;

	__cpuid(eax, ebx, ecx, edx);

}



/*

 * CPUID functions returning a single datum

 */

static inline unsigned int cpuid_eax(unsigned int op)

{

	unsigned int eax, ebx, ecx, edx;



	cpuid(op, &eax, &ebx, &ecx, &edx);



	return eax;

}



static inline unsigned int cpuid_ebx(unsigned int op)

{

	unsigned int eax, ebx, ecx, edx;



	cpuid(op, &eax, &ebx, &ecx, &edx);



	return ebx;

}



static inline unsigned int cpuid_ecx(unsigned int op)

{

	unsigned int eax, ebx, ecx, edx;



	cpuid(op, &eax, &ebx, &ecx, &edx);



	return ecx;

}



static inline unsigned int cpuid_edx(unsigned int op)

{

	unsigned int eax, ebx, ecx, edx;



	cpuid(op, &eax, &ebx, &ecx, &edx);



	return edx;

}



static __always_inline bool cpuid_function_is_indexed(u32 function)

{

	switch (function) {
@@ -31,4 +150,22 @@ static __always_inline bool cpuid_function_is_indexed(u32 function) 
	return false;

}



#define for_each_possible_hypervisor_cpuid_base(function) \

	for (function = 0x40000000; function < 0x40010000; function += 0x100)



static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)

{

	uint32_t base, eax, signature[3];



	for_each_possible_hypervisor_cpuid_base(base) {

		cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);



		if (!memcmp(sig, signature, 12) &&

		    (leaves == 0 || ((eax - base) >= leaves)))

			return base;

	}



	return 0;

}



#endif /* _ASM_X86_CPUID_H */

arch/x86/include/asm/disabled-features.h

+7 −1
Original line number Diff line number Diff line
@@ -81,6 +81,12 @@ 
# define DISABLE_SGX	(1 << (X86_FEATURE_SGX & 31))

#endif



#ifdef CONFIG_XEN_PV

# define DISABLE_XENPV		0

#else

# define DISABLE_XENPV		(1 << (X86_FEATURE_XENPV & 31))

#endif



#ifdef CONFIG_INTEL_TDX_GUEST

# define DISABLE_TDX_GUEST	0

#else
@@ -98,7 +104,7 @@ 
#define DISABLED_MASK5	0

#define DISABLED_MASK6	0

#define DISABLED_MASK7	(DISABLE_PTI)

#define DISABLED_MASK8	(DISABLE_TDX_GUEST)

#define DISABLED_MASK8	(DISABLE_XENPV|DISABLE_TDX_GUEST)

#define DISABLED_MASK9	(DISABLE_SGX)

#define DISABLED_MASK10	0

#define DISABLED_MASK11	(DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET)

arch/x86/include/asm/entry-common.h

+2 −2
Original line number Diff line number Diff line
@@ -24,8 +24,8 @@ static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) 
		/*

		 * For !SMAP hardware we patch out CLAC on entry.

		 */

		if (boot_cpu_has(X86_FEATURE_SMAP) ||

		    (IS_ENABLED(CONFIG_64BIT) && boot_cpu_has(X86_FEATURE_XENPV)))

		if (cpu_feature_enabled(X86_FEATURE_SMAP) ||

		    cpu_feature_enabled(X86_FEATURE_XENPV))

			mask |= X86_EFLAGS_AC;



		WARN_ON_ONCE(flags & mask);

arch/x86/include/asm/memtype.h

+2 −3
Original line number Diff line number Diff line
@@ -6,9 +6,8 @@ 
#include <asm/pgtable_types.h>



extern bool pat_enabled(void);

extern void pat_disable(const char *reason);

extern void pat_init(void);

extern void init_cache_modes(void);

extern void pat_bp_init(void);

extern void pat_cpu_init(void);



extern int memtype_reserve(u64 start, u64 end,

		enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm);