Commit 3ee81e02 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Krzysztof Kozlowski
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dt-bindings: memory: tegra20: mc: Document new interconnect property 



Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201104164923.21238-7-digetx@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent e51a59f0

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt

+3 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ Required properties: 
  IOMMU specifier needed to encode an address. GART supports only a single

  address space that is shared by all devices, therefore no additional

  information needed for the address encoding.

- #interconnect-cells : Should be 1. This cell represents memory client.

  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>.



Example:

	mc: memory-controller@7000f000 {
@@ -27,6 +29,7 @@ Example: 
		interrupts = <GIC_SPI 77 0x04>;

		#reset-cells = <1>;

		#iommu-cells = <0>;

		#interconnect-cells = <1>;

	};



	video-codec@6001a000 {