Commit 3ed741db authored by Lars-Peter Clausen's avatar Lars-Peter Clausen Committed by Stephen Boyd
Browse files

clk: vc5: Use `clamp()` to restrict PLL range 



The VCO frequency needs to be within a certain range and the driver
enforces this.

Make use of the clamp macro to implement this instead of open-coding it.
This makes the code a bit shorter and also semanticly stronger.

Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230114233500.3294789-1-lars@metafoo.de


Reviewed-by: default avatarLuca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 1b929c02

drivers/clk/clk-versaclock5.c

+1 −4
Original line number Diff line number Diff line
@@ -449,10 +449,7 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
	u32 div_int;

	u64 div_frc;



	if (rate < VC5_PLL_VCO_MIN)

		rate = VC5_PLL_VCO_MIN;

	if (rate > VC5_PLL_VCO_MAX)

		rate = VC5_PLL_VCO_MAX;

	rate = clamp(rate, VC5_PLL_VCO_MIN, VC5_PLL_VCO_MAX);



	/* Determine integer part, which is 12 bit wide */

	div_int = rate / *parent_rate;