Commit 3ebb9fdf authored by Conor Dooley's avatar Conor Dooley Committed by Stephen Boyd
Browse files

dt-bindings: clk: mpfs document msspll dri registers 



As there are two sections of registers that are responsible for clock
configuration on the PolarFire SoC: add the dynamic reconfiguration
interface section to the binding & describe what each of the sections
are used for.

Fixes: 2145bb68 ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding")
Reviewed-by: default avatarDaire McNamara <daire.mcnamara@microchip.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220413075835.3354193-5-conor.dooley@microchip.com


Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 2b6190c8

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

+11 −2
Original line number Diff line number Diff line
@@ -22,7 +22,16 @@ properties: 
    const: microchip,mpfs-clkcfg



  reg:

    maxItems: 1

    items:

      - description: |

          clock config registers:

          These registers contain enable, reset & divider tables for the, cpu,

          axi, ahb and rtc/mtimer reference clocks as well as enable and reset

          for the peripheral clocks.

      - description: |

          mss pll dri registers:

          Block of registers responsible for dynamic reconfiguration of the mss

          pll



  clocks:

    maxItems: 1
@@ -51,7 +60,7 @@ examples: 
            #size-cells = <2>;

            clkcfg: clock-controller@20002000 {

                compatible = "microchip,mpfs-clkcfg";

                reg = <0x0 0x20002000 0x0 0x1000>;

                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;

                clocks = <&ref>;

                #clock-cells = <1>;

        };