Commit 3eba620e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cleanups_for_v6.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cleanups from Borislav Petkov:

 - The usual round of smaller fixes and cleanups all over the tree

* tag 'x86_cleanups_for_v6.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Include the header of init_ia32_feat_ctl()'s prototype
  x86/uaccess: Improve __try_cmpxchg64_user_asm() for x86_32
  x86: Fix various duplicate-word comment typos
  x86/boot: Remove superfluous type casting from arch/x86/boot/bitops.h
parents 193e2268 30ea703a

arch/x86/boot/bitops.h

+2 −2
Original line number Diff line number Diff line
@@ -19,13 +19,13 @@ 


static inline bool constant_test_bit(int nr, const void *addr)

{

	const u32 *p = (const u32 *)addr;

	const u32 *p = addr;

	return ((1UL << (nr & 31)) & (p[nr >> 5])) != 0;

}

static inline bool variable_test_bit(int nr, const void *addr)

{

	bool v;

	const u32 *p = (const u32 *)addr;

	const u32 *p = addr;



	asm("btl %2,%1" CC_SET(c) : CC_OUT(c) (v) : "m" (*p), "Ir" (nr));

	return v;

arch/x86/include/asm/uaccess.h

+6 −5
Original line number Diff line number Diff line
@@ -448,7 +448,7 @@ do { \ 


#ifdef CONFIG_X86_32

/*

 * Unlike the normal CMPXCHG, hardcode ECX for both success/fail and error.

 * Unlike the normal CMPXCHG, use output GPR for both success/fail and error.

 * There are only six GPRs available and four (EAX, EBX, ECX, and EDX) are

 * hardcoded by CMPXCHG8B, leaving only ESI and EDI.  If the compiler uses

 * both ESI and EDI for the memory operand, compilation will fail if the error
@@ -461,11 +461,12 @@ do { \ 
	__typeof__(*(_ptr)) __new = (_new);				\

	asm volatile("\n"						\

		     "1: " LOCK_PREFIX "cmpxchg8b %[ptr]\n"		\

		     "mov $0, %%ecx\n\t"				\

		     "setz %%cl\n"					\

		     "mov $0, %[result]\n\t"				\

		     "setz %b[result]\n"				\

		     "2:\n"						\

		     _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, %%ecx) \

		     : [result]"=c" (__result),				\

		     _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG,	\

					   %[result])			\

		     : [result] "=q" (__result),			\

		       "+A" (__old),					\

		       [ptr] "+m" (*_ptr)				\

		     : "b" ((u32)__new),				\

arch/x86/kernel/amd_gart_64.c

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static u32 *iommu_gatt_base; /* Remapping table */ 
 * of only flushing when an mapping is reused. With it true the GART is

 * flushed for every mapping. Problem is that doing the lazy flush seems

 * to trigger bugs with some popular PCI cards, in particular 3ware (but

 * has been also also seen with Qlogic at least).

 * has been also seen with Qlogic at least).

 */

static int iommu_fullflush = 1;

arch/x86/kernel/aperture_64.c

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
/*

 * Using 512M as goal, in case kexec will load kernel_big

 * that will do the on-position decompress, and could overlap with

 * with the gart aperture that is used.

 * the gart aperture that is used.

 * Sequence:

 * kernel_small

 * ==> kexec (with kdump trigger path or gart still enabled)

arch/x86/kernel/cpu/feat_ctl.c

+1 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

#include <linux/tboot.h>



#include <asm/cpu.h>

#include <asm/cpufeature.h>

#include <asm/msr-index.h>

#include <asm/processor.h>

#include <asm/vmx.h>

#include "cpu.h"



#undef pr_fmt

#define pr_fmt(fmt)	"x86/cpu: " fmt