Commit 3ea355b2 authored by Matthew Auld's avatar Matthew Auld
Browse files

drm/i915/clflush: fixup handling of cache_dirty 



In theory if clflush_work_create() somehow fails here, and we don't yet
have mm.pages populated then we end up resetting cache_dirty, which is
likely wrong, since that will potentially skip the flush-on-acquire, if
it was needed.

It looks like intel_user_framebuffer_dirty() can arrive here before the
pages are populated.

v2(Thomas):
  - Move setting cache_dirty out of the async portion, also add a
    comment for why that should still be safe.
v3:
  - Add Thomas' irc r-b

Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211027161813.3094681-1-matthew.auld@intel.com
parent cad7109a

drivers/gpu/drm/i915/gem/i915_gem_clflush.c

+9 −1
Original line number Diff line number Diff line
@@ -109,12 +109,20 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, 
						I915_FENCE_GFP);

		dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma);

		dma_fence_work_commit(&clflush->base);

		/*

		 * We must have successfully populated the pages(since we are

		 * holding a pin on the pages as per the flush worker) to reach

		 * this point, which must mean we have already done the required

		 * flush-on-acquire, hence resetting cache_dirty here should be

		 * safe.

		 */

		obj->cache_dirty = false;

	} else if (obj->mm.pages) {

		__do_clflush(obj);

		obj->cache_dirty = false;

	} else {

		GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);

	}



	obj->cache_dirty = false;

	return true;

}