Commit 3e8d74cb authored by Saaem Rizvi's avatar Saaem Rizvi Committed by Alex Deucher
Browse files

drm/amd/display: Trigger DIO FIFO resync on commit streams 



[WHY]
Currently, there is an intermittent issue where a screen can either go
blank or be corrupted.

[HOW]
To resolve the issue we trigger the ramping logic for DIO FIFO so that
it goes back up to the correct speed.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarSaaem Rizvi <syedsaaem.rizvi@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 91b38ca1

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+3 −0
Original line number Diff line number Diff line
@@ -2291,6 +2291,9 @@ enum dc_status dce110_apply_ctx_to_hw( 


		if (DC_OK != status)

			return status;



		if (hws->funcs.resync_fifo_dccg_dio)

			hws->funcs.resync_fifo_dccg_dio(hws, dc, context);

	}



	if (dc->fbc_compressor)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

+3 −1
Original line number Diff line number Diff line
@@ -208,7 +208,9 @@ 
#define DCCG314_REG_FIELD_LIST(type) \

	type DSCCLK3_DTO_PHASE;\

	type DSCCLK3_DTO_MODULO;\

	type DSCCLK3_DTO_ENABLE;

	type DSCCLK3_DTO_ENABLE;\

	type DENTIST_DISPCLK_RDIVIDER;\

	type DENTIST_DISPCLK_WDIVIDER;



#define DCCG32_REG_FIELD_LIST(type) \

	type DPSTREAMCLK0_EN;\

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c

+11 −0
Original line number Diff line number Diff line
@@ -45,6 +45,16 @@ 
#define DC_LOGGER \

	dccg->ctx->logger



static void dccg314_trigger_dio_fifo_resync(

	struct dccg *dccg)

{

	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

	uint32_t dispclk_rdivider_value = 0;



	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value);

	REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);

}



static void dccg314_get_pixel_rate_div(

		struct dccg *dccg,

		uint32_t otg_inst,
@@ -357,6 +367,7 @@ static const struct dccg_funcs dccg314_funcs = { 
	.disable_dsc = dccg31_disable_dscclk,

	.enable_dsc = dccg31_enable_dscclk,

	.set_pixel_rate_div = dccg314_set_pixel_rate_div,

	.trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync,

	.set_valid_pixel_rate = dccg314_set_valid_pixel_rate,

};

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h

+4 −1
Original line number Diff line number Diff line
@@ -192,7 +192,10 @@ 
	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh)

	DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\

	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\

	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\

	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh)



struct dccg *dccg314_create(

	struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c

+27 −0
Original line number Diff line number Diff line
@@ -390,6 +390,33 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 
				pix_per_cycle);

}



void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)

{

	uint8_t i;

	struct pipe_ctx *pipe = NULL;

	bool otg_disabled[MAX_PIPES] = {false};



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		pipe = &dc->current_state->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;



		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {

			pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);

			reset_sync_context_for_pipe(dc, context, i);

			otg_disabled[i] = true;

		}

	}



	hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (otg_disabled[i])

			pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);

	}

}



void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)

{

	if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)