Commit 3e7f2f29 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.12-next-soc' of... 

Merge tag 'v5.12-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

- add MT8183 support to mutex driver

MMSYS:
- use per SoC array to describe the possible routing
- add support for MT8183

Power management domains:
- fix the case of a domain fails to get added
- add names for each power domain to make debugging easier

PMIC wrapper:
- add support for PMIC wrapper with integrated arbiter
- add support for MT8192/MT6873

* tag 'v5.12-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: pm-domains: Add a power domain names for mt8167
  soc: mediatek: pm-domains: Add a power domain names for mt8192
  soc: mediatek: pm-domains: Add a power domain names for mt8183
  soc: mediatek: pm-domains: Add a meaningful power domain name
  soc: mediatek: Make symbol 'mtk_mutex_driver' static
  soc: mediatek: mmsys: Add mt8183 mmsys routing table
  soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs
  dt-bindings: mediatek: add compatible for MT6873/8192 pwrap
  soc: mediatek: pwrap: add arbiter capability
  soc: mediatek: pwrap: use BIT() macro
  soc: mediatek: pm-domains: Fix missing error code in scpsys_add_subdomain()
  soc: mediatek: mmsys: Use an array for setting the routing registers
  soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
  soc: mediatek: add mtk mutex support for MT8183

Link: https://lore.kernel.org/r/c47d4bdd-9e05-c0de-bacb-3a262fed936d@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 66f3431a 60d93f64

Documentation/devicetree/bindings/soc/mediatek/pwrap.txt

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Required properties in pwrap device node. 
	"mediatek,mt6765-pwrap" for MT6765 SoCs

	"mediatek,mt6779-pwrap" for MT6779 SoCs

	"mediatek,mt6797-pwrap" for MT6797 SoCs

	"mediatek,mt6873-pwrap" for MT6873/8192 SoCs

	"mediatek,mt7622-pwrap" for MT7622 SoCs

	"mediatek,mt8135-pwrap" for MT8135 SoCs

	"mediatek,mt8173-pwrap" for MT8173 SoCs

drivers/soc/mediatek/mt8167-pm-domains.h

+7 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 


static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {

	[MT8167_POWER_DOMAIN_MM] = {

		.name = "mm",

		.sta_mask = PWR_STATUS_DISP,

		.ctl_offs = SPM_DIS_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),
@@ -26,6 +27,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.caps = MTK_SCPD_ACTIVE_WAKEUP,

	},

	[MT8167_POWER_DOMAIN_VDEC] = {

		.name = "vdec",

		.sta_mask = PWR_STATUS_VDEC,

		.ctl_offs = SPM_VDE_PWR_CON,

		.sram_pdn_bits = GENMASK(8, 8),
@@ -33,6 +35,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.caps = MTK_SCPD_ACTIVE_WAKEUP,

	},

	[MT8167_POWER_DOMAIN_ISP] = {

		.name = "isp",

		.sta_mask = PWR_STATUS_ISP,

		.ctl_offs = SPM_ISP_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),
@@ -40,6 +43,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		.caps = MTK_SCPD_ACTIVE_WAKEUP,

	},

	[MT8167_POWER_DOMAIN_MFG_ASYNC] = {

		.name = "mfg_async",

		.sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,

		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,

		.sram_pdn_bits = 0,
@@ -50,18 +54,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 
		},

	},

	[MT8167_POWER_DOMAIN_MFG_2D] = {

		.name = "mfg_2d",

		.sta_mask = MT8167_PWR_STATUS_MFG_2D,

		.ctl_offs = SPM_MFG_2D_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},

	[MT8167_POWER_DOMAIN_MFG] = {

		.name = "mfg",

		.sta_mask = PWR_STATUS_MFG,

		.ctl_offs = SPM_MFG_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},

	[MT8167_POWER_DOMAIN_CONN] = {

		.name = "conn",

		.sta_mask = PWR_STATUS_CONN,

		.ctl_offs = SPM_CONN_PWR_CON,

		.sram_pdn_bits = GENMASK(8, 8),

drivers/soc/mediatek/mt8173-pm-domains.h

+10 −0
Original line number Diff line number Diff line
@@ -12,24 +12,28 @@ 


static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {

	[MT8173_POWER_DOMAIN_VDEC] = {

		.name = "vdec",

		.sta_mask = PWR_STATUS_VDEC,

		.ctl_offs = SPM_VDE_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

	},

	[MT8173_POWER_DOMAIN_VENC] = {

		.name = "venc",

		.sta_mask = PWR_STATUS_VENC,

		.ctl_offs = SPM_VEN_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},

	[MT8173_POWER_DOMAIN_ISP] = {

		.name = "isp",

		.sta_mask = PWR_STATUS_ISP,

		.ctl_offs = SPM_ISP_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

	},

	[MT8173_POWER_DOMAIN_MM] = {

		.name = "mm",

		.sta_mask = PWR_STATUS_DISP,

		.ctl_offs = SPM_DIS_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),
@@ -40,18 +44,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		},

	},

	[MT8173_POWER_DOMAIN_VENC_LT] = {

		.name = "venc_lt",

		.sta_mask = PWR_STATUS_VENC_LT,

		.ctl_offs = SPM_VEN2_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},

	[MT8173_POWER_DOMAIN_AUDIO] = {

		.name = "audio",

		.sta_mask = PWR_STATUS_AUDIO,

		.ctl_offs = SPM_AUDIO_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},

	[MT8173_POWER_DOMAIN_USB] = {

		.name = "usb",

		.sta_mask = PWR_STATUS_USB,

		.ctl_offs = SPM_USB_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),
@@ -59,18 +66,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.caps = MTK_SCPD_ACTIVE_WAKEUP,

	},

	[MT8173_POWER_DOMAIN_MFG_ASYNC] = {

		.name = "mfg_async",

		.sta_mask = PWR_STATUS_MFG_ASYNC,

		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = 0,

	},

	[MT8173_POWER_DOMAIN_MFG_2D] = {

		.name = "mfg_2d",

		.sta_mask = PWR_STATUS_MFG_2D,

		.ctl_offs = SPM_MFG_2D_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

	},

	[MT8173_POWER_DOMAIN_MFG] = {

		.name = "mfg",

		.sta_mask = PWR_STATUS_MFG,

		.ctl_offs = SPM_MFG_PWR_CON,

		.sram_pdn_bits = GENMASK(13, 8),

drivers/soc/mediatek/mt8183-mmsys.h

0 → 100644
+54 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */



#ifndef __SOC_MEDIATEK_MT8183_MMSYS_H

#define __SOC_MEDIATEK_MT8183_MMSYS_H



#define MT8183_DISP_OVL0_MOUT_EN		0xf00

#define MT8183_DISP_OVL0_2L_MOUT_EN		0xf04

#define MT8183_DISP_OVL1_2L_MOUT_EN		0xf08

#define MT8183_DISP_DITHER0_MOUT_EN		0xf0c

#define MT8183_DISP_PATH0_SEL_IN		0xf24

#define MT8183_DISP_DSI0_SEL_IN			0xf2c

#define MT8183_DISP_DPI0_SEL_IN			0xf30

#define MT8183_DISP_RDMA0_SOUT_SEL_IN		0xf50

#define MT8183_DISP_RDMA1_SOUT_SEL_IN		0xf54



#define MT8183_OVL0_MOUT_EN_OVL0_2L		BIT(4)

#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0	BIT(0)

#define MT8183_OVL1_2L_MOUT_EN_RDMA1		BIT(4)

#define MT8183_DITHER0_MOUT_IN_DSI0		BIT(0)

#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L	0x1

#define MT8183_DSI0_SEL_IN_RDMA0		0x1

#define MT8183_DSI0_SEL_IN_RDMA1		0x3

#define MT8183_DPI0_SEL_IN_RDMA0		0x1

#define MT8183_DPI0_SEL_IN_RDMA1		0x2

#define MT8183_RDMA0_SOUT_COLOR0		0x1

#define MT8183_RDMA1_SOUT_DSI0			0x1



static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,

		MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L

	}, {

		DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,

		MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0

	}, {

		DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,

		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1

	}, {

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0

	}, {

		DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,

		MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,

		MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0

	}

};



#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */

drivers/soc/mediatek/mt8183-pm-domains.h

+15 −0
Original line number Diff line number Diff line
@@ -12,12 +12,14 @@ 


static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {

	[MT8183_POWER_DOMAIN_AUDIO] = {

		.name = "audio",

		.sta_mask = PWR_STATUS_AUDIO,

		.ctl_offs = 0x0314,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

	},

	[MT8183_POWER_DOMAIN_CONN] = {

		.name = "conn",

		.sta_mask = PWR_STATUS_CONN,

		.ctl_offs = 0x032c,

		.sram_pdn_bits = 0,
@@ -28,12 +30,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		},

	},

	[MT8183_POWER_DOMAIN_MFG_ASYNC] = {

		.name = "mfg_async",

		.sta_mask = PWR_STATUS_MFG_ASYNC,

		.ctl_offs = 0x0334,

		.sram_pdn_bits = 0,

		.sram_pdn_ack_bits = 0,

	},

	[MT8183_POWER_DOMAIN_MFG] = {

		.name = "mfg",

		.sta_mask = PWR_STATUS_MFG,

		.ctl_offs = 0x0338,

		.sram_pdn_bits = GENMASK(8, 8),
@@ -41,18 +45,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.caps = MTK_SCPD_DOMAIN_SUPPLY,

	},

	[MT8183_POWER_DOMAIN_MFG_CORE0] = {

		.name = "mfg_core0",

		.sta_mask = BIT(7),

		.ctl_offs = 0x034c,

		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

	},

	[MT8183_POWER_DOMAIN_MFG_CORE1] = {

		.name = "mfg_core1",

		.sta_mask = BIT(20),

		.ctl_offs = 0x0310,

		.sram_pdn_bits = GENMASK(8, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

	},

	[MT8183_POWER_DOMAIN_MFG_2D] = {

		.name = "mfg_2d",

		.sta_mask = PWR_STATUS_MFG_2D,

		.ctl_offs = 0x0348,

		.sram_pdn_bits = GENMASK(8, 8),
@@ -65,6 +72,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		},

	},

	[MT8183_POWER_DOMAIN_DISP] = {

		.name = "disp",

		.sta_mask = PWR_STATUS_DISP,

		.ctl_offs = 0x030c,

		.sram_pdn_bits = GENMASK(8, 8),
@@ -83,6 +91,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		},

	},

	[MT8183_POWER_DOMAIN_CAM] = {

		.name = "cam",

		.sta_mask = BIT(25),

		.ctl_offs = 0x0344,

		.sram_pdn_bits = GENMASK(9, 8),
@@ -105,6 +114,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		},

	},

	[MT8183_POWER_DOMAIN_ISP] = {

		.name = "isp",

		.sta_mask = PWR_STATUS_ISP,

		.ctl_offs = 0x0308,

		.sram_pdn_bits = GENMASK(9, 8),
@@ -127,6 +137,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		},

	},

	[MT8183_POWER_DOMAIN_VDEC] = {

		.name = "vdec",

		.sta_mask = BIT(31),

		.ctl_offs = 0x0300,

		.sram_pdn_bits = GENMASK(8, 8),
@@ -139,6 +150,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		},

	},

	[MT8183_POWER_DOMAIN_VENC] = {

		.name = "venc",

		.sta_mask = PWR_STATUS_VENC,

		.ctl_offs = 0x0304,

		.sram_pdn_bits = GENMASK(11, 8),
@@ -151,6 +163,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		},

	},

	[MT8183_POWER_DOMAIN_VPU_TOP] = {

		.name = "vpu_top",

		.sta_mask = BIT(26),

		.ctl_offs = 0x0324,

		.sram_pdn_bits = GENMASK(8, 8),
@@ -177,6 +190,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		},

	},

	[MT8183_POWER_DOMAIN_VPU_CORE0] = {

		.name = "vpu_core0",

		.sta_mask = BIT(27),

		.ctl_offs = 0x33c,

		.sram_pdn_bits = GENMASK(11, 8),
@@ -194,6 +208,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 
		.caps = MTK_SCPD_SRAM_ISO,

	},

	[MT8183_POWER_DOMAIN_VPU_CORE1] = {

		.name = "vpu_core1",

		.sta_mask = BIT(28),

		.ctl_offs = 0x0340,

		.sram_pdn_bits = GENMASK(11, 8),