Commit 3e50523f authored by Tomer Maimon's avatar Tomer Maimon Committed by Joel Stanley
Browse files

ARM: dts: nuvoton: Modify clock parameters 



Modify NPCM7xx device tree clock parameter to clock constants that
define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file.

Signed-off-by: default avatarTomer Maimon <tmaimon77@gmail.com>
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20200929131807.15378-2-tmaimon77@gmail.com


Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
parent 3650b228

arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi

+10 −9
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
// Copyright 2018 Google, Inc.



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>



/ {

	#address-cells = <1>;
@@ -80,7 +81,7 @@ 
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

			cache-unified;

			cache-level = <2>;

			clocks = <&clk 10>;

			clocks = <&clk NPCM7XX_CLK_AXI>;

			arm,shared-override;

		};
@@ -120,7 +121,7 @@ 
				compatible = "nuvoton,npcm750-timer";

				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x8000 0x50>;

				clocks = <&clk 5>;

				clocks = <&clk NPCM7XX_CLK_TIMER>;

			};



			watchdog0: watchdog@801C {
@@ -128,7 +129,7 @@ 
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x801C 0x4>;

				status = "disabled";

				clocks = <&clk 5>;

				clocks = <&clk NPCM7XX_CLK_TIMER>;

			};



			watchdog1: watchdog@901C {
@@ -136,7 +137,7 @@ 
				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x901C 0x4>;

				status = "disabled";

				clocks = <&clk 5>;

				clocks = <&clk NPCM7XX_CLK_TIMER>;

			};



			watchdog2: watchdog@a01C {
@@ -144,13 +145,13 @@ 
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xa01C 0x4>;

				status = "disabled";

				clocks = <&clk 5>;

				clocks = <&clk NPCM7XX_CLK_TIMER>;

			};



			serial0: serial@1000 {

				compatible = "nuvoton,npcm750-uart";

				reg = <0x1000 0x1000>;

				clocks = <&clk 6>;

				clocks = <&clk NPCM7XX_CLK_UART>;

				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

				reg-shift = <2>;

				status = "disabled";
@@ -159,7 +160,7 @@ 
			serial1: serial@2000 {

				compatible = "nuvoton,npcm750-uart";

				reg = <0x2000 0x1000>;

				clocks = <&clk 6>;

				clocks = <&clk NPCM7XX_CLK_UART>;

				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

				reg-shift = <2>;

				status = "disabled";
@@ -168,7 +169,7 @@ 
			serial2: serial@3000 {

				compatible = "nuvoton,npcm750-uart";

				reg = <0x3000 0x1000>;

				clocks = <&clk 6>;

				clocks = <&clk NPCM7XX_CLK_UART>;

				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

				reg-shift = <2>;

				status = "disabled";
@@ -177,7 +178,7 @@ 
			serial3: serial@4000 {

				compatible = "nuvoton,npcm750-uart";

				reg = <0x4000 0x1000>;

				clocks = <&clk 6>;

				clocks = <&clk NPCM7XX_CLK_UART>;

				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

				reg-shift = <2>;

				status = "disabled";

arch/arm/boot/dts/nuvoton-npcm750.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			clocks = <&clk 0>;

			clocks = <&clk NPCM7XX_CLK_CPU>;

			clock-names = "clk_cpu";

			reg = <0>;

			next-level-cache = <&l2>;
@@ -26,7 +26,7 @@ 
		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			clocks = <&clk 0>;

			clocks = <&clk NPCM7XX_CLK_CPU>;

			clock-names = "clk_cpu";

			reg = <1>;

			next-level-cache = <&l2>;
@@ -38,7 +38,7 @@ 
			reg = <0x3fe600 0x20>;

			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |

						  IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&clk 5>;

			clocks = <&clk NPCM7XX_CLK_AHB>;

		};

	};

};