Commit 3e287bec authored by Russell King's avatar Russell King
Browse files

ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5 



Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather
than r2/r3.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 8dfe7ac9

arch/arm/kernel/entry-armv.S

+2 −4
Original line number Diff line number Diff line
@@ -56,14 +56,12 @@ 
	.endm



	.macro	dabt_helper

	mov	r2, r4

	mov	r3, r5



	@

	@ Call the processor-specific abort handler:

	@

	@  r2 - aborted context pc

	@  r3 - aborted context cpsr

	@  r4 - aborted context pc

	@  r5 - aborted context psr

	@

	@ The abort handler must return the aborted address in r0, and

	@ the fault status register in r1.  r9 must be preserved.

arch/arm/mm/abort-ev4.S

+3 −5
Original line number Diff line number Diff line
@@ -3,8 +3,8 @@ 
/*

 * Function: v4_early_abort

 *

 * Params  : r2 = address of aborted instruction

 *         : r3 = saved SPSR

 * Params  : r4 = aborted context pc

 *	   : r5 = aborted context psr

 *

 * Returns : r0 = address of abort

 *	   : r1 = FSR, bit 11 = write
@@ -21,10 +21,8 @@ 
ENTRY(v4_early_abort)

	mrc	p15, 0, r1, c5, c0, 0		@ get FSR

	mrc	p15, 0, r0, c6, c0, 0		@ get FAR

	ldr	r3, [r2]			@ read aborted ARM instruction

	ldr	r3, [r4]			@ read aborted ARM instruction

	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR

	tst	r3, #1 << 20			@ L = 1 -> write?

	orreq	r1, r1, #1 << 11		@ yes.

	mov	pc, lr

arch/arm/mm/abort-ev4t.S

+4 −4
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ 
/*

 * Function: v4t_early_abort

 *

 * Params  : r2 = address of aborted instruction

 *         : r3 = saved SPSR

 * Params  : r4 = aborted context pc

 *	   : r5 = aborted context psr

 *

 * Returns : r0 = address of abort

 *	   : r1 = FSR, bit 11 = write
@@ -22,8 +22,8 @@ 
ENTRY(v4t_early_abort)

	mrc	p15, 0, r1, c5, c0, 0		@ get FSR

	mrc	p15, 0, r0, c6, c0, 0		@ get FAR

	do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3

	ldreq	r3, [r2]			@ read aborted ARM instruction

	do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3

	ldreq	r3, [r4]			@ read aborted ARM instruction

	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR

	tst	r3, #1 << 20			@ check write

	orreq	r1, r1, #1 << 11

arch/arm/mm/abort-ev5t.S

+4 −4
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ 
/*

 * Function: v5t_early_abort

 *

 * Params  : r2 = address of aborted instruction

 *         : r3 = saved SPSR

 * Params  : r4 = aborted context pc

 *	   : r5 = aborted context psr

 *

 * Returns : r0 = address of abort

 *	   : r1 = FSR, bit 11 = write
@@ -22,8 +22,8 @@ 
ENTRY(v5t_early_abort)

	mrc	p15, 0, r1, c5, c0, 0		@ get FSR

	mrc	p15, 0, r0, c6, c0, 0		@ get FAR

	do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3

	ldreq	r3, [r2]			@ read aborted ARM instruction

	do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3

	ldreq	r3, [r4]			@ read aborted ARM instruction

	bic	r1, r1, #1 << 11		@ clear bits 11 of FSR

	do_ldrd_abort tmp=r2, insn=r3

	tst	r3, #1 << 20			@ check write

arch/arm/mm/abort-ev5tj.S

+5 −7
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ 
/*

 * Function: v5tj_early_abort

 *

 * Params  : r2 = address of aborted instruction

 *         : r3 = saved SPSR

 * Params  : r4 = aborted context pc

 *	   : r5 = aborted context psr

 *

 * Returns : r0 = address of abort

 *	   : r1 = FSR, bit 11 = write
@@ -23,13 +23,11 @@ ENTRY(v5tj_early_abort) 
	mrc	p15, 0, r1, c5, c0, 0		@ get FSR

	mrc	p15, 0, r0, c6, c0, 0		@ get FAR

	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR

	tst	r3, #PSR_J_BIT			@ Java?

	tst	r5, #PSR_J_BIT			@ Java?

	movne	pc, lr

	do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3

	ldreq	r3, [r2]			@ read aborted ARM instruction

	do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3

	ldreq	r3, [r4]			@ read aborted ARM instruction

	do_ldrd_abort tmp=r2, insn=r3

	tst	r3, #1 << 20			@ L = 0 -> write

	orreq	r1, r1, #1 << 11		@ yes.

	mov	pc, lr