Commit 3e18ff4b authored by Pu Lehui's avatar Pu Lehui Committed by Alexei Starovoitov
Browse files

riscv, bpf: Support signed div/mod insns 



Add support signed div/mod instructions for RV64.

Signed-off-by: default avatarPu Lehui <pulehui@huawei.com>
Acked-by: default avatarBjörn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/r/20230824095001.3408573-6-pulehui@huaweicloud.com


Signed-off-by: default avatarAlexei Starovoitov <ast@kernel.org>
parent d9839f16

arch/riscv/net/bpf_jit.h

+20 −0
Original line number Diff line number Diff line
@@ -431,11 +431,21 @@ static inline u32 rv_mulhu(u8 rd, u8 rs1, u8 rs2) 
	return rv_r_insn(1, rs2, rs1, 3, rd, 0x33);

}



static inline u32 rv_div(u8 rd, u8 rs1, u8 rs2)

{

	return rv_r_insn(1, rs2, rs1, 4, rd, 0x33);

}



static inline u32 rv_divu(u8 rd, u8 rs1, u8 rs2)

{

	return rv_r_insn(1, rs2, rs1, 5, rd, 0x33);

}



static inline u32 rv_rem(u8 rd, u8 rs1, u8 rs2)

{

	return rv_r_insn(1, rs2, rs1, 6, rd, 0x33);

}



static inline u32 rv_remu(u8 rd, u8 rs1, u8 rs2)

{

	return rv_r_insn(1, rs2, rs1, 7, rd, 0x33);
@@ -776,11 +786,21 @@ static inline u32 rv_mulw(u8 rd, u8 rs1, u8 rs2) 
	return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b);

}



static inline u32 rv_divw(u8 rd, u8 rs1, u8 rs2)

{

	return rv_r_insn(1, rs2, rs1, 4, rd, 0x3b);

}



static inline u32 rv_divuw(u8 rd, u8 rs1, u8 rs2)

{

	return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b);

}



static inline u32 rv_remw(u8 rd, u8 rs1, u8 rs2)

{

	return rv_r_insn(1, rs2, rs1, 6, rd, 0x3b);

}



static inline u32 rv_remuw(u8 rd, u8 rs1, u8 rs2)

{

	return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b);

arch/riscv/net/bpf_jit_comp64.c

+20 −6
Original line number Diff line number Diff line
@@ -1107,12 +1107,18 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 
		break;

	case BPF_ALU | BPF_DIV | BPF_X:

	case BPF_ALU64 | BPF_DIV | BPF_X:

		if (off)

			emit(is64 ? rv_div(rd, rd, rs) : rv_divw(rd, rd, rs), ctx);

		else

			emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx);

		if (!is64 && !aux->verifier_zext)

			emit_zext_32(rd, ctx);

		break;

	case BPF_ALU | BPF_MOD | BPF_X:

	case BPF_ALU64 | BPF_MOD | BPF_X:

		if (off)

			emit(is64 ? rv_rem(rd, rd, rs) : rv_remw(rd, rd, rs), ctx);

		else

			emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx);

		if (!is64 && !aux->verifier_zext)

			emit_zext_32(rd, ctx);
@@ -1284,6 +1290,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 
	case BPF_ALU | BPF_DIV | BPF_K:

	case BPF_ALU64 | BPF_DIV | BPF_K:

		emit_imm(RV_REG_T1, imm, ctx);

		if (off)

			emit(is64 ? rv_div(rd, rd, RV_REG_T1) :

			     rv_divw(rd, rd, RV_REG_T1), ctx);

		else

			emit(is64 ? rv_divu(rd, rd, RV_REG_T1) :

			     rv_divuw(rd, rd, RV_REG_T1), ctx);

		if (!is64 && !aux->verifier_zext)
@@ -1292,6 +1302,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 
	case BPF_ALU | BPF_MOD | BPF_K:

	case BPF_ALU64 | BPF_MOD | BPF_K:

		emit_imm(RV_REG_T1, imm, ctx);

		if (off)

			emit(is64 ? rv_rem(rd, rd, RV_REG_T1) :

			     rv_remw(rd, rd, RV_REG_T1), ctx);

		else

			emit(is64 ? rv_remu(rd, rd, RV_REG_T1) :

			     rv_remuw(rd, rd, RV_REG_T1), ctx);

		if (!is64 && !aux->verifier_zext)