Commit 3df9bdd4 authored by Yong Wu's avatar Yong Wu Committed by Joerg Roedel
Browse files

iommu/mediatek: Add a gap for the iova regions 



As the removed property in the vcodec dt-binding, the property is:
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;

The length is 0xfff0_0000 rather than 0x1_0000_0000, this means it
requires 1M as a gap. This is because the end address for some vcodec
HW is (address + size). If the size is 4G, the end address may be
0x2_0000_0000, and the width for vcodec register only is 32, then the
HW may get the ZERO address.

Currently the consumer's dma-ranges property doesn't work, IOMMU
has to consider this case. Add a bigger gap(8M) for all the regions
to avoid it.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230411093144.2690-9-yong.wu@mediatek.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent f5d4233a

drivers/iommu/mtk_iommu.c

+7 −5
Original line number Diff line number Diff line
@@ -332,8 +332,10 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */ 


#define for_each_m4u(data, head)  list_for_each_entry(data, head, list)



#define MTK_IOMMU_IOVA_SZ_4G		(SZ_4G - SZ_8M) /* 8M as gap */



static const struct mtk_iommu_iova_region single_domain[] = {

	{.iova_base = 0,		.size = SZ_4G},

	{.iova_base = 0,		.size = MTK_IOMMU_IOVA_SZ_4G},

};



#define MT8192_MULTI_REGION_NR_MAX	6
@@ -342,11 +344,11 @@ static const struct mtk_iommu_iova_region single_domain[] = { 
				 MT8192_MULTI_REGION_NR_MAX : 1)



static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = {

	{ .iova_base = 0x0,		.size = SZ_4G},		/* 0 ~ 4G */

	{ .iova_base = 0x0,		.size = MTK_IOMMU_IOVA_SZ_4G},	/* 0 ~ 4G,  */

	#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)

	{ .iova_base = SZ_4G,		.size = SZ_4G},		/* 4G ~ 8G */

	{ .iova_base = SZ_4G * 2,	.size = SZ_4G},		/* 8G ~ 12G */

	{ .iova_base = SZ_4G * 3,	.size = SZ_4G},		/* 12G ~ 16G */

	{ .iova_base = SZ_4G,		.size = MTK_IOMMU_IOVA_SZ_4G},	/* 4G ~ 8G */

	{ .iova_base = SZ_4G * 2,	.size = MTK_IOMMU_IOVA_SZ_4G},	/* 8G ~ 12G */

	{ .iova_base = SZ_4G * 3,	.size = MTK_IOMMU_IOVA_SZ_4G},	/* 12G ~ 16G */



	{ .iova_base = 0x240000000ULL,	.size = 0x4000000},	/* CCU0 */

	{ .iova_base = 0x244000000ULL,	.size = 0x4000000},	/* CCU1 */