Commit 3de810ac authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/dt' 

- Add MT8188 and MT8195 to mediatek-gen3 DT binding (Jianjun Wang)

- Add 'clock-names' back to fu740 DT binding (Conor Dooley)

- Add 'clocks', 'clock-names', 'dma-ranges' to microchip DT binding (Conor
  Dooley)

- Add 'aggre0' and 'aggre1' clocks to qcom DT binding (Krishna chaitanya
  chundru)

* remotes/lorenzo/pci/dt:
  dt-bindings: pci: QCOM Add missing sc7280 aggre0, aggre1 clocks
  dt-bindings: PCI: microchip,pcie-host: fix missing dma-ranges
  dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties
  dt-bindings: PCI: fu740-pci: fix missing clock-names
  dt-bindings: PCI: mediatek-gen3: Add support for MT8188 and MT8195
parents 84aabff8 1abbe04a

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

+11 −2
Original line number Diff line number Diff line
@@ -48,7 +48,13 @@ allOf: 


properties:

  compatible:

    const: mediatek,mt8192-pcie

    oneOf:

      - items:

          - enum:

              - mediatek,mt8188-pcie

              - mediatek,mt8195-pcie

          - const: mediatek,mt8192-pcie

      - const: mediatek,mt8192-pcie



  reg:

    maxItems: 1
@@ -84,7 +90,9 @@ properties: 
      - const: tl_96m

      - const: tl_32k

      - const: peri_26m

      - const: top_133m

      - enum:

          - top_133m        # for MT8192

          - peri_mem        # for MT8188/MT8195



  assigned-clocks:

    maxItems: 1
@@ -126,6 +134,7 @@ required: 
  - interrupts

  - ranges

  - clocks

  - clock-names

  - '#interrupt-cells'

  - interrupt-controller

Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml

+31 −0
Original line number Diff line number Diff line
@@ -25,6 +25,33 @@ properties: 
      - const: cfg

      - const: apb



  clocks:

    description:

      Fabric Interface Controllers, FICs, are the interface between the FPGA

      fabric and the core complex on PolarFire SoC. The FICs require two clocks,

      one from each side of the interface. The "FIC clocks" described by this

      property are on the core complex side & communication through a FIC is not

      possible unless it's corresponding clock is enabled. A clock must be

      enabled for each of the interfaces the root port is connected through.

      This could in theory be all 4 interfaces, one interface or any combination

      in between.

    minItems: 1

    items:

      - description: FIC0's clock

      - description: FIC1's clock

      - description: FIC2's clock

      - description: FIC3's clock



  clock-names:

    description:

      As any FIC connection combination is possible, the names should match the

      order in the clocks property and take the form "ficN" where N is a number

      0-3

    minItems: 1

    maxItems: 4

    items:

      pattern: '^fic[0-3]$'



  interrupts:

    minItems: 1

    items:
@@ -40,6 +67,10 @@ properties: 
  ranges:

    maxItems: 1



  dma-ranges:

    minItems: 1

    maxItems: 6



  msi-controller:

    description: Identifies the node as an MSI controller.

Documentation/devicetree/bindings/pci/qcom,pcie.yaml

+6 −4
Original line number Diff line number Diff line
@@ -54,11 +54,11 @@ properties: 
  # Platform constraints are described later.

  clocks:

    minItems: 3

    maxItems: 12

    maxItems: 13



  clock-names:

    minItems: 3

    maxItems: 12

    maxItems: 13



  resets:

    minItems: 1
@@ -424,8 +424,8 @@ allOf: 
    then:

      properties:

        clocks:

          minItems: 11

          maxItems: 11

          minItems: 13

          maxItems: 13

        clock-names:

          items:

            - const: pipe # PIPE clock
@@ -439,6 +439,8 @@ allOf: 
            - const: slave_q2a # Slave Q2A clock

            - const: tbu # PCIe TBU clock

            - const: ddrss_sf_tbu # PCIe SF TBU clock

            - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock

            - const: aggre1 # Aggre NoC PCIe1 AXI clock

        resets:

          maxItems: 1

        reset-names:

Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml

+8 −0
Original line number Diff line number Diff line
@@ -51,6 +51,12 @@ properties: 
    description: A phandle to the PCIe power up reset line.

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: pcie_aux



  pwren-gpios:

    description: Should specify the GPIO for controlling the PCI bus device power on.

    maxItems: 1
@@ -66,6 +72,7 @@ required: 
  - interrupt-map-mask

  - interrupt-map

  - clocks

  - clock-names

  - resets

  - pwren-gpios

  - reset-gpios
@@ -104,6 +111,7 @@ examples: 
                            <0x0 0x0 0x0 0x2 &plic0 58>,

                            <0x0 0x0 0x0 0x3 &plic0 59>,

                            <0x0 0x0 0x0 0x4 &plic0 60>;

            clock-names = "pcie_aux";

            clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;

            resets = <&prci 4>;

            pwren-gpios = <&gpio 5 0>;