Commit 3dd2401b authored by Weilong Chen's avatar Weilong Chen Committed by Yuan Can
Browse files

cache: Workaround HiSilicon Linxicore DC CVAU 

ascend inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8OX47


CVE: NA

-------------------------------------

Linxicore's L1/L2 cache is inclusive, and the data is consistent.
Any change of L1 does not require DC operation to brush CL in L1 to L2.
It's safe that don't clean data cache by address to point of unification.

Some of the Linxicore report wrong value to kernel. Without reporting this
IDC featrue, the kernel needs to flush icache as well as dcache, causes
performance degradation.

Signed-off-by: default avatarWeilong Chen <chenweilong@huawei.com>
parent d63a6b3e

Documentation/arch/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -205,6 +205,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #162100125      | HISILICON_ERRATUM_162100125 |

+----------------+-----------------+-----------------+-----------------------------+

| Hisilicon      | LINXICORE9100   | #1980005        | HISILICON_ERRATUM_1980005   |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo/Falkor v1  | E1003           | QCOM_FALKOR_ERRATUM_1003    |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -1170,6 +1170,16 @@ config HISILICON_ERRATUM_162100125 


	  If unsure, say Y.



config HISILICON_ERRATUM_1980005

	bool "Hisilicon erratum 1980005: IDC support"

	default n

	help

	  Some of the Hisilicon linxicore support idc but report wrong value to

	  the kernel, which result to the unnecessary cache flush, leading to

	  performance degradation.



	  If unsure, say N.



config QCOM_FALKOR_ERRATUM_1003

	bool "Falkor E1003: Incorrect translation due to ASID change"

	default y

arch/arm64/include/asm/cache.h

+9 −0
Original line number Diff line number Diff line
@@ -112,6 +112,15 @@ int cache_line_size(void); 
static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)

{

	u32 ctr = read_cpuid_cachetype();

#ifdef CONFIG_HISILICON_ERRATUM_1980005

	static const struct midr_range idc_support_list[] = {

		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),

		MIDR_REV(MIDR_HISI_LINXICORE9100, 1, 0),

		{ /* sentinel */ }

	};

	if (is_midr_in_range_list(read_cpuid_id(), idc_support_list))

		ctr |= BIT(CTR_EL0_IDC_SHIFT);

#endif



	if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {

		u64 clidr = read_sysreg(clidr_el1);

arch/arm64/kernel/cpu_errata.c

+33 −0
Original line number Diff line number Diff line
@@ -60,6 +60,30 @@ is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 
	return model == entry->midr_range.model;

}



#ifdef CONFIG_HISILICON_ERRATUM_1980005

static bool

hisilicon_1980005_match(const struct arm64_cpu_capabilities *entry,

			int scope)

{

	static const struct midr_range idc_support_list[] = {

		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),

		MIDR_REV(MIDR_HISI_LINXICORE9100, 1, 0),

		{ /* sentinel */ }

	};



	return is_midr_in_range_list(read_cpuid_id(), idc_support_list);

}



static void

hisilicon_1980005_enable(const struct arm64_cpu_capabilities *__unused)

{

	__set_bit(ARM64_HAS_CACHE_IDC, system_cpucaps);

	arm64_ftr_reg_ctrel0.sys_val |= BIT(CTR_EL0_IDC_SHIFT);

	arm64_ftr_reg_ctrel0.strict_mask &= ~BIT(CTR_EL0_IDC_SHIFT);

	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);

}

#endif



static bool

has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,

			  int scope)
@@ -567,6 +591,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus),

	},

#endif

#ifdef CONFIG_HISILICON_ERRATUM_1980005

	{

		.desc = "Hisilicon erratum 1980005 (IDC)",

		.capability = ARM64_WORKAROUND_HISILICON_1980005,

		.matches = hisilicon_1980005_match,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.cpu_enable = hisilicon_1980005_enable,

	},

#endif

#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

	{

		.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",

arch/arm64/tools/cpucaps

+1 −0
Original line number Diff line number Diff line
@@ -102,3 +102,4 @@ WORKAROUND_REPEAT_TLBI 
WORKAROUND_SPECULATIVE_AT

WORKAROUND_HISILICON_ERRATUM_162100125

WORKAROUND_HISI_HIP08_RU_PREFETCH

WORKAROUND_HISILICON_1980005