cache: Workaround HiSilicon Linxicore DC CVAU

ascend inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8OX47


CVE: NA

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Linxicore's L1/L2 cache is inclusive, and the data is consistent.
Any change of L1 does not require DC operation to brush CL in L1 to L2.
It's safe that don't clean data cache by address to point of unification.

Some of the Linxicore report wrong value to kernel. Without reporting this
IDC featrue, the kernel needs to flush icache as well as dcache, causes
performance degradation.

Signed-off-by: Weilong Chen <chenweilong@huawei.com>