Unverified Commit 3dcce5b3 authored by Mark Brown's avatar Mark Brown
Browse files

spi-geni-qcom: Add SPI device mode support for GENI 

Merge series from Praveen Talari <quic_ptalari@quicinc.com>:

This series adds spi device mode functionality to geni based Qupv3.
The common header file contains spi slave related registers and masks.

Praveen Talari (2):
  soc: qcom: geni-se: Add SPI Device mode support for GENI based QuPv3
  spi: spi-geni-qcom: Add SPI Device mode support for GENI based QuPv3
---
v6 -> v7:
- Corrected author mail

v5 -> v6:
- Added code comments
- Dropped get_spi_master api

v4 -> v5:
- Addressed review comments in driver

v3 -> v4:
- Used existing property spi-slave
- Hence dropped dt-binding changes

v2 -> v3:
- Modified commit message
- Addressed comment on dt-binding

v1 -> v2:
- Added dt-binding change for spi slave
- Modified commit message
- Addressed review comments in driver

 drivers/spi/spi-geni-qcom.c      | 53 ++++++++++++++++++++++++++++----
 include/linux/soc/qcom/geni-se.h |  9 ++++++
 2 files changed, 56 insertions(+), 6 deletions(-)

--
2.17.1
parents 6c7a8640 d7f74cc3

drivers/spi/spi-geni-qcom.c

+47 −6
Original line number Original line Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/platform_device.h>

#include <linux/platform_device.h>

#include <linux/pm_opp.h>

#include <linux/pm_opp.h>

#include <linux/pm_runtime.h>

#include <linux/pm_runtime.h>

#include <linux/property.h>

#include <linux/soc/qcom/geni-se.h>

#include <linux/soc/qcom/geni-se.h>

#include <linux/spi/spi.h>

#include <linux/spi/spi.h>

#include <linux/spinlock.h>

#include <linux/spinlock.h>
@@ -52,6 +53,9 @@ 
#define SPI_CS_CLK_DELAY_MSK		GENMASK(19, 10)

#define SPI_CS_CLK_DELAY_MSK		GENMASK(19, 10)

#define SPI_CS_CLK_DELAY_SHFT		10

#define SPI_CS_CLK_DELAY_SHFT		10





#define SE_SPI_SLAVE_EN				(0x2BC)

#define SPI_SLAVE_EN				BIT(0)



/* M_CMD OP codes for SPI */

/* M_CMD OP codes for SPI */

#define SPI_TX_ONLY		1

#define SPI_TX_ONLY		1

#define SPI_RX_ONLY		2

#define SPI_RX_ONLY		2
@@ -99,6 +103,16 @@ struct spi_geni_master { 
	int cur_xfer_mode;

	int cur_xfer_mode;

};

};





static void spi_slv_setup(struct spi_geni_master *mas)

{

	struct geni_se *se = &mas->se;



	writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);

	writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);

	writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);

	dev_dbg(mas->dev, "spi slave setup done\n");

}



static int get_spi_clk_cfg(unsigned int speed_hz,

static int get_spi_clk_cfg(unsigned int speed_hz,

			struct spi_geni_master *mas,

			struct spi_geni_master *mas,

			unsigned int *clk_idx,

			unsigned int *clk_idx,
@@ -140,12 +154,22 @@ static void handle_se_timeout(struct spi_master *spi, 
	const struct spi_transfer *xfer;

	const struct spi_transfer *xfer;





	spin_lock_irq(&mas->lock);

	spin_lock_irq(&mas->lock);

	reinit_completion(&mas->cancel_done);

	if (mas->cur_xfer_mode == GENI_SE_FIFO)

	if (mas->cur_xfer_mode == GENI_SE_FIFO)

		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);

		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);





	xfer = mas->cur_xfer;

	xfer = mas->cur_xfer;

	mas->cur_xfer = NULL;

	mas->cur_xfer = NULL;



	if (spi->slave) {

		/*

		 * skip CMD Cancel sequnece since spi slave

		 * doesn`t support CMD Cancel sequnece

		 */

		spin_unlock_irq(&mas->lock);

		goto unmap_if_dma;

	}



	reinit_completion(&mas->cancel_done);

	geni_se_cancel_m_cmd(se);

	geni_se_cancel_m_cmd(se);

	spin_unlock_irq(&mas->lock);

	spin_unlock_irq(&mas->lock);
@@ -542,6 +566,10 @@ static bool geni_can_dma(struct spi_controller *ctlr, 
	if (mas->cur_xfer_mode == GENI_GPI_DMA)

	if (mas->cur_xfer_mode == GENI_GPI_DMA)

		return true;

		return true;





	/* Set SE DMA mode for SPI slave. */

	if (ctlr->slave)

		return true;



	len = get_xfer_len_in_words(xfer, mas);

	len = get_xfer_len_in_words(xfer, mas);

	fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word;

	fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word;
@@ -619,6 +647,7 @@ static void spi_geni_release_dma_chan(struct spi_geni_master *mas) 




static int spi_geni_init(struct spi_geni_master *mas)

static int spi_geni_init(struct spi_geni_master *mas)

{

{

	struct spi_master *spi = dev_get_drvdata(mas->dev);

	struct geni_se *se = &mas->se;

	struct geni_se *se = &mas->se;

	unsigned int proto, major, minor, ver;

	unsigned int proto, major, minor, ver;

	u32 spi_tx_cfg, fifo_disable;

	u32 spi_tx_cfg, fifo_disable;
@@ -627,7 +656,14 @@ static int spi_geni_init(struct spi_geni_master *mas) 
	pm_runtime_get_sync(mas->dev);

	pm_runtime_get_sync(mas->dev);





	proto = geni_se_read_proto(se);

	proto = geni_se_read_proto(se);

	if (proto != GENI_SE_SPI) {



	if (spi->slave) {

		if (proto != GENI_SE_SPI_SLAVE) {

			dev_err(mas->dev, "Invalid proto %d\n", proto);

			goto out_pm;

		}

		spi_slv_setup(mas);

	} else if (proto != GENI_SE_SPI) {

		dev_err(mas->dev, "Invalid proto %d\n", proto);

		dev_err(mas->dev, "Invalid proto %d\n", proto);

		goto out_pm;

		goto out_pm;

	}

	}
@@ -679,9 +715,11 @@ static int spi_geni_init(struct spi_geni_master *mas) 
	}

	}





	/* We always control CS manually */

	/* We always control CS manually */

	if (!spi->slave) {

		spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);

		spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);

		spi_tx_cfg &= ~CS_TOGGLE;

		spi_tx_cfg &= ~CS_TOGGLE;

		writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);

		writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);

	}





out_pm:

out_pm:

	pm_runtime_put(mas->dev);

	pm_runtime_put(mas->dev);
@@ -1074,6 +1112,9 @@ static int spi_geni_probe(struct platform_device *pdev) 
	pm_runtime_set_autosuspend_delay(&pdev->dev, 250);

	pm_runtime_set_autosuspend_delay(&pdev->dev, 250);

	pm_runtime_enable(dev);

	pm_runtime_enable(dev);





	if (device_property_read_bool(&pdev->dev, "spi-slave"))

		spi->slave = true;



	ret = geni_icc_get(&mas->se, NULL);

	ret = geni_icc_get(&mas->se, NULL);

	if (ret)

	if (ret)

		goto spi_geni_probe_runtime_disable;

		goto spi_geni_probe_runtime_disable;
@@ -1094,7 +1135,7 @@ static int spi_geni_probe(struct platform_device *pdev) 
	 * for dma (gsi) mode, the gsi will set cs based on params passed in

	 * for dma (gsi) mode, the gsi will set cs based on params passed in

	 * TRE

	 * TRE

	 */

	 */

	if (mas->cur_xfer_mode == GENI_SE_FIFO)

	if (!spi->slave && mas->cur_xfer_mode == GENI_SE_FIFO)

		spi->set_cs = spi_geni_set_cs;

		spi->set_cs = spi_geni_set_cs;





	/*

	/*

include/linux/soc/qcom/geni-se.h

+9 −0
Original line number Original line Diff line number Diff line
@@ -35,6 +35,7 @@ enum geni_se_protocol_type { 
	GENI_SE_UART,

	GENI_SE_UART,

	GENI_SE_I2C,

	GENI_SE_I2C,

	GENI_SE_I3C,

	GENI_SE_I3C,

	GENI_SE_SPI_SLAVE,

};

};





struct geni_wrapper;

struct geni_wrapper;
@@ -73,12 +74,14 @@ struct geni_se { 




/* Common SE registers */

/* Common SE registers */

#define GENI_FORCE_DEFAULT_REG		0x20

#define GENI_FORCE_DEFAULT_REG		0x20

#define GENI_OUTPUT_CTRL		0x24

#define SE_GENI_STATUS			0x40

#define SE_GENI_STATUS			0x40

#define GENI_SER_M_CLK_CFG		0x48

#define GENI_SER_M_CLK_CFG		0x48

#define GENI_SER_S_CLK_CFG		0x4c

#define GENI_SER_S_CLK_CFG		0x4c

#define GENI_IF_DISABLE_RO		0x64

#define GENI_IF_DISABLE_RO		0x64

#define GENI_FW_REVISION_RO		0x68

#define GENI_FW_REVISION_RO		0x68

#define SE_GENI_CLK_SEL			0x7c

#define SE_GENI_CLK_SEL			0x7c

#define SE_GENI_CFG_SEQ_START		0x84

#define SE_GENI_DMA_MODE_EN		0x258

#define SE_GENI_DMA_MODE_EN		0x258

#define SE_GENI_M_CMD0			0x600

#define SE_GENI_M_CMD0			0x600

#define SE_GENI_M_CMD_CTRL_REG		0x604

#define SE_GENI_M_CMD_CTRL_REG		0x604
@@ -111,6 +114,9 @@ struct geni_se { 
/* GENI_FORCE_DEFAULT_REG fields */

/* GENI_FORCE_DEFAULT_REG fields */

#define FORCE_DEFAULT	BIT(0)

#define FORCE_DEFAULT	BIT(0)





/* GENI_OUTPUT_CTRL fields */

#define GENI_IO_MUX_0_EN		BIT(0)



/* GENI_STATUS fields */

/* GENI_STATUS fields */

#define M_GENI_CMD_ACTIVE		BIT(0)

#define M_GENI_CMD_ACTIVE		BIT(0)

#define S_GENI_CMD_ACTIVE		BIT(12)

#define S_GENI_CMD_ACTIVE		BIT(12)
@@ -130,6 +136,9 @@ struct geni_se { 
/* GENI_CLK_SEL fields */

/* GENI_CLK_SEL fields */

#define CLK_SEL_MSK			GENMASK(2, 0)

#define CLK_SEL_MSK			GENMASK(2, 0)





/* SE_GENI_CFG_SEQ_START fields */

#define START_TRIGGER			BIT(0)



/* SE_GENI_DMA_MODE_EN */

/* SE_GENI_DMA_MODE_EN */

#define GENI_DMA_MODE_EN		BIT(0)

#define GENI_DMA_MODE_EN		BIT(0)