Commit 3dc8a1f6 authored by Dongdong Liu's avatar Dongdong Liu Committed by Bjorn Helgaas
Browse files

PCI: Support BAR sizes up to 8TB 

Current kernel reports that BARs larger than 128GB, e.g., this 4TB BAR, are
disabled:

    pci 0000:01:00.0: disabling BAR 4: [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000)

Increase the maximum BAR size from 128GB to 8TB for future expansion.

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/20220118092117.10089-1-liudongdong3@huawei.com


Signed-off-by: default avatarDongdong Liu <liudongdong3@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent e783362e

drivers/pci/setup-bus.c

+1 −1
Original line number Diff line number Diff line
@@ -994,7 +994,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 
{

	struct pci_dev *dev;

	resource_size_t min_align, align, size, size0, size1;

	resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */

	resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */

	int order, max_order;

	struct resource *b_res = find_bus_resource_of_type(bus,

					mask | IORESOURCE_PREFETCH, type);