Loading drivers/scsi/qla2xxx/qla_init.c +24 −46 Original line number Diff line number Diff line Loading @@ -925,6 +925,16 @@ qla2x00_setup_chip(scsi_qla_host_t *ha) { int rval; uint32_t srisc_address = 0; struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; unsigned long flags; if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { /* Disable SRAM, Instruction RAM and GP RAM parity. */ spin_lock_irqsave(&ha->hardware_lock, flags); WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); RD_REG_WORD(®->hccr); spin_unlock_irqrestore(&ha->hardware_lock, flags); } /* Load firmware sequences */ rval = ha->isp_ops->load_risc(ha, &srisc_address); Loading Loading @@ -968,6 +978,19 @@ qla2x00_setup_chip(scsi_qla_host_t *ha) } } if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { /* Enable proper parity. */ spin_lock_irqsave(&ha->hardware_lock, flags); if (IS_QLA2300(ha)) /* SRAM parity */ WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); else /* SRAM, Instruction RAM and GP RAM parity */ WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); RD_REG_WORD(®->hccr); spin_unlock_irqrestore(&ha->hardware_lock, flags); } if (rval) { DEBUG2_3(printk("scsi(%ld): Setup chip **** FAILED ****.\n", ha->host_no)); Loading Loading @@ -3344,60 +3367,15 @@ static int qla2x00_restart_isp(scsi_qla_host_t *ha) { uint8_t status = 0; struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; unsigned long flags = 0; uint32_t wait_time; /* If firmware needs to be loaded */ if (qla2x00_isp_firmware(ha)) { ha->flags.online = 0; if (!(status = ha->isp_ops->chip_diag(ha))) { if (IS_QLA2100(ha) || IS_QLA2200(ha)) { if (!(status = ha->isp_ops->chip_diag(ha))) status = qla2x00_setup_chip(ha); goto done; } spin_lock_irqsave(&ha->hardware_lock, flags); if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha) && !IS_QLA25XX(ha)) { /* * Disable SRAM, Instruction RAM and GP RAM * parity. */ WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); RD_REG_WORD(®->hccr); } spin_unlock_irqrestore(&ha->hardware_lock, flags); status = qla2x00_setup_chip(ha); spin_lock_irqsave(&ha->hardware_lock, flags); if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha) && !IS_QLA25XX(ha)) { /* Enable proper parity */ if (IS_QLA2300(ha)) /* SRAM parity */ WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x1)); else /* * SRAM, Instruction RAM and GP RAM * parity. */ WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x7)); RD_REG_WORD(®->hccr); } spin_unlock_irqrestore(&ha->hardware_lock, flags); } } done: if (!status && !(status = qla2x00_init_rings(ha))) { clear_bit(RESET_MARKER_NEEDED, &ha->dpc_flags); if (!(status = qla2x00_fw_ready(ha))) { Loading drivers/scsi/qla2xxx/qla_os.c +0 −12 Original line number Diff line number Diff line Loading @@ -1780,18 +1780,6 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) WRT_REG_WORD(®->isp.semaphore, 0); WRT_REG_WORD(®->isp.hccr, HCCR_CLR_RISC_INT); WRT_REG_WORD(®->isp.hccr, HCCR_CLR_HOST_INT); /* Enable proper parity */ if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) { if (IS_QLA2300(ha)) /* SRAM parity */ WRT_REG_WORD(®->isp.hccr, (HCCR_ENABLE_PARITY + 0x1)); else /* SRAM, Instruction RAM and GP RAM parity */ WRT_REG_WORD(®->isp.hccr, (HCCR_ENABLE_PARITY + 0x7)); } } spin_unlock_irqrestore(&ha->hardware_lock, flags); Loading Loading
drivers/scsi/qla2xxx/qla_init.c +24 −46 Original line number Diff line number Diff line Loading @@ -925,6 +925,16 @@ qla2x00_setup_chip(scsi_qla_host_t *ha) { int rval; uint32_t srisc_address = 0; struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; unsigned long flags; if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { /* Disable SRAM, Instruction RAM and GP RAM parity. */ spin_lock_irqsave(&ha->hardware_lock, flags); WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); RD_REG_WORD(®->hccr); spin_unlock_irqrestore(&ha->hardware_lock, flags); } /* Load firmware sequences */ rval = ha->isp_ops->load_risc(ha, &srisc_address); Loading Loading @@ -968,6 +978,19 @@ qla2x00_setup_chip(scsi_qla_host_t *ha) } } if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { /* Enable proper parity. */ spin_lock_irqsave(&ha->hardware_lock, flags); if (IS_QLA2300(ha)) /* SRAM parity */ WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); else /* SRAM, Instruction RAM and GP RAM parity */ WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); RD_REG_WORD(®->hccr); spin_unlock_irqrestore(&ha->hardware_lock, flags); } if (rval) { DEBUG2_3(printk("scsi(%ld): Setup chip **** FAILED ****.\n", ha->host_no)); Loading Loading @@ -3344,60 +3367,15 @@ static int qla2x00_restart_isp(scsi_qla_host_t *ha) { uint8_t status = 0; struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; unsigned long flags = 0; uint32_t wait_time; /* If firmware needs to be loaded */ if (qla2x00_isp_firmware(ha)) { ha->flags.online = 0; if (!(status = ha->isp_ops->chip_diag(ha))) { if (IS_QLA2100(ha) || IS_QLA2200(ha)) { if (!(status = ha->isp_ops->chip_diag(ha))) status = qla2x00_setup_chip(ha); goto done; } spin_lock_irqsave(&ha->hardware_lock, flags); if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha) && !IS_QLA25XX(ha)) { /* * Disable SRAM, Instruction RAM and GP RAM * parity. */ WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); RD_REG_WORD(®->hccr); } spin_unlock_irqrestore(&ha->hardware_lock, flags); status = qla2x00_setup_chip(ha); spin_lock_irqsave(&ha->hardware_lock, flags); if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha) && !IS_QLA25XX(ha)) { /* Enable proper parity */ if (IS_QLA2300(ha)) /* SRAM parity */ WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x1)); else /* * SRAM, Instruction RAM and GP RAM * parity. */ WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x7)); RD_REG_WORD(®->hccr); } spin_unlock_irqrestore(&ha->hardware_lock, flags); } } done: if (!status && !(status = qla2x00_init_rings(ha))) { clear_bit(RESET_MARKER_NEEDED, &ha->dpc_flags); if (!(status = qla2x00_fw_ready(ha))) { Loading
drivers/scsi/qla2xxx/qla_os.c +0 −12 Original line number Diff line number Diff line Loading @@ -1780,18 +1780,6 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) WRT_REG_WORD(®->isp.semaphore, 0); WRT_REG_WORD(®->isp.hccr, HCCR_CLR_RISC_INT); WRT_REG_WORD(®->isp.hccr, HCCR_CLR_HOST_INT); /* Enable proper parity */ if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) { if (IS_QLA2300(ha)) /* SRAM parity */ WRT_REG_WORD(®->isp.hccr, (HCCR_ENABLE_PARITY + 0x1)); else /* SRAM, Instruction RAM and GP RAM parity */ WRT_REG_WORD(®->isp.hccr, (HCCR_ENABLE_PARITY + 0x7)); } } spin_unlock_irqrestore(&ha->hardware_lock, flags); Loading