Loading include/asm-sh/cpu-sh3/timer.h +2 −4 Original line number Diff line number Diff line Loading @@ -23,8 +23,7 @@ * --------------------------------------------------------------------------- */ #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ !defined(CONFIG_CPU_SUBTYPE_SH7727) #if !defined(CONFIG_CPU_SUBTYPE_SH7720) #define TMU_TOCR 0xfffffe90 /* Byte access */ #endif Loading Loading @@ -58,8 +57,7 @@ #define TMU2_TCOR 0xfffffeac /* Long access */ #define TMU2_TCNT 0xfffffeb0 /* Long access */ #define TMU2_TCR 0xfffffeb4 /* Word access */ #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ !defined(CONFIG_CPU_SUBTYPE_SH7727) #if !defined(CONFIG_CPU_SUBTYPE_SH7720) #define TMU2_TCPR2 0xfffffeb8 /* Long access */ #endif #endif Loading Loading
include/asm-sh/cpu-sh3/timer.h +2 −4 Original line number Diff line number Diff line Loading @@ -23,8 +23,7 @@ * --------------------------------------------------------------------------- */ #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ !defined(CONFIG_CPU_SUBTYPE_SH7727) #if !defined(CONFIG_CPU_SUBTYPE_SH7720) #define TMU_TOCR 0xfffffe90 /* Byte access */ #endif Loading Loading @@ -58,8 +57,7 @@ #define TMU2_TCOR 0xfffffeac /* Long access */ #define TMU2_TCNT 0xfffffeb0 /* Long access */ #define TMU2_TCR 0xfffffeb4 /* Word access */ #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ !defined(CONFIG_CPU_SUBTYPE_SH7727) #if !defined(CONFIG_CPU_SUBTYPE_SH7720) #define TMU2_TCPR2 0xfffffeb8 /* Long access */ #endif #endif Loading