dt-bindings: msm: disp: add yaml schemas for DPU bindings (3d7a0dd8) · Commits · EulixOS / Software / Kernel

Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml

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		# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Qualcomm Display DPU dt properties for SC7180 target

		maintainers:
		- Krishna Manikandan <mkrishn@codeaurora.org>

		description: \|
		Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
		sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
		bindings of MDSS and DPU are mentioned for SC7180 target.

		properties:
		compatible:
		items:
		- const: qcom,sc7180-mdss

		reg:
		maxItems: 1

		reg-names:
		const: mdss

		power-domains:
		maxItems: 1

		clocks:
		items:
		- description: Display AHB clock from gcc
		- description: Display AHB clock from dispcc
		- description: Display core clock

		clock-names:
		items:
		- const: iface
		- const: ahb
		- const: core

		interrupts:
		maxItems: 1

		interrupt-controller: true

		"#address-cells": true

		"#size-cells": true

		"#interrupt-cells":
		const: 1

		iommus:
		items:
		- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0

		ranges: true

		interconnects:
		items:
		- description: Interconnect path specifying the port ids for data bus

		interconnect-names:
		const: mdp0-mem

		patternProperties:
		"^display-controller@[0-9a-f]+$":
		type: object
		description: Node containing the properties of DPU.

		properties:
		compatible:
		items:
		- const: qcom,sc7180-dpu

		reg:
		items:
		- description: Address offset and size for mdp register set
		- description: Address offset and size for vbif register set

		reg-names:
		items:
		- const: mdp
		- const: vbif

		clocks:
		items:
		- description: Display hf axi clock
		- description: Display ahb clock
		- description: Display rotator clock
		- description: Display lut clock
		- description: Display core clock
		- description: Display vsync clock

		clock-names:
		items:
		- const: bus
		- const: iface
		- const: rot
		- const: lut
		- const: core
		- const: vsync

		interrupts:
		maxItems: 1

		power-domains:
		maxItems: 1

		operating-points-v2: true

		ports:
		$ref: /schemas/graph.yaml#/properties/ports
		description: \|
		Contains the list of output ports from DPU device. These ports
		connect to interfaces that are external to the DPU hardware,
		such as DSI, DP etc. Each output port contains an endpoint that
		describes how it is connected to an external interface.

		properties:
		port@0:
		$ref: /schemas/graph.yaml#/properties/port
		description: DPU_INTF1 (DSI1)

		port@2:
		$ref: /schemas/graph.yaml#/properties/port
		description: DPU_INTF0 (DP)

		required:
		- port@0

		required:
		- compatible
		- reg
		- reg-names
		- clocks
		- interrupts
		- power-domains
		- operating-points-v2
		- ports

		required:
		- compatible
		- reg
		- reg-names
		- power-domains
		- clocks
		- interrupts
		- interrupt-controller
		- iommus
		- ranges

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
		#include <dt-bindings/clock/qcom,gcc-sc7180.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/interconnect/qcom,sdm845.h>
		#include <dt-bindings/power/qcom-rpmpd.h>

		display-subsystem@ae00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "qcom,sc7180-mdss";
		reg = <0xae00000 0x1000>;
		reg-names = "mdss";
		power-domains = <&dispcc MDSS_GDSC>;
		clocks = <&gcc GCC_DISP_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK>;
		clock-names = "iface", "ahb", "core";

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;

		interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
		interconnect-names = "mdp0-mem";

		iommus = <&apps_smmu 0x800 0x2>;
		ranges;

		display-controller@ae01000 {
		compatible = "qcom,sc7180-dpu";
		reg = <0x0ae01000 0x8f000>,
		<0x0aeb0000 0x2008>;

		reg-names = "mdp", "vbif";

		clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
		<&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_ROT_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK>,
		<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
		clock-names = "bus", "iface", "rot", "lut", "core",
		"vsync";

		interrupt-parent = <&mdss>;
		interrupts = <0>;
		power-domains = <&rpmhpd SC7180_CX>;
		operating-points-v2 = <&mdp_opp_table>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dpu_intf1_out: endpoint {
		remote-endpoint = <&dsi0_in>;
		};
		};

		port@2 {
		reg = <2>;
		dpu_intf0_out: endpoint {
		remote-endpoint = <&dp_in>;
		};
		};
		};
		};
		};
		...

Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml

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		# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Qualcomm Display DPU dt properties for SDM845 target

		maintainers:
		- Krishna Manikandan <mkrishn@codeaurora.org>

		description: \|
		Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
		sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
		bindings of MDSS and DPU are mentioned for SDM845 target.

		properties:
		compatible:
		items:
		- const: qcom,sdm845-mdss

		reg:
		maxItems: 1

		reg-names:
		const: mdss

		power-domains:
		maxItems: 1

		clocks:
		items:
		- description: Display AHB clock from gcc
		- description: Display AXI clock
		- description: Display core clock

		clock-names:
		items:
		- const: iface
		- const: bus
		- const: core

		interrupts:
		maxItems: 1

		interrupt-controller: true

		"#address-cells": true

		"#size-cells": true

		"#interrupt-cells":
		const: 1

		iommus:
		items:
		- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
		- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1

		ranges: true

		patternProperties:
		"^display-controller@[0-9a-f]+$":
		type: object
		description: Node containing the properties of DPU.

		properties:
		compatible:
		items:
		- const: qcom,sdm845-dpu

		reg:
		items:
		- description: Address offset and size for mdp register set
		- description: Address offset and size for vbif register set

		reg-names:
		items:
		- const: mdp
		- const: vbif

		clocks:
		items:
		- description: Display ahb clock
		- description: Display axi clock
		- description: Display core clock
		- description: Display vsync clock

		clock-names:
		items:
		- const: iface
		- const: bus
		- const: core
		- const: vsync

		interrupts:
		maxItems: 1

		power-domains:
		maxItems: 1

		operating-points-v2: true
		ports:
		$ref: /schemas/graph.yaml#/properties/ports
		description: \|
		Contains the list of output ports from DPU device. These ports
		connect to interfaces that are external to the DPU hardware,
		such as DSI, DP etc. Each output port contains an endpoint that
		describes how it is connected to an external interface.

		properties:
		port@0:
		$ref: /schemas/graph.yaml#/properties/port
		description: DPU_INTF1 (DSI1)

		port@1:
		$ref: /schemas/graph.yaml#/properties/port
		description: DPU_INTF2 (DSI2)

		required:
		- port@0
		- port@1

		required:
		- compatible
		- reg
		- reg-names
		- clocks
		- interrupts
		- power-domains
		- operating-points-v2
		- ports

		required:
		- compatible
		- reg
		- reg-names
		- power-domains
		- clocks
		- interrupts
		- interrupt-controller
		- iommus
		- ranges

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
		#include <dt-bindings/clock/qcom,gcc-sdm845.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/power/qcom-rpmpd.h>

		display-subsystem@ae00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "qcom,sdm845-mdss";
		reg = <0x0ae00000 0x1000>;
		reg-names = "mdss";
		power-domains = <&dispcc MDSS_GDSC>;

		clocks = <&gcc GCC_DISP_AHB_CLK>,
		<&gcc GCC_DISP_AXI_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK>;
		clock-names = "iface", "bus", "core";

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;

		iommus = <&apps_smmu 0x880 0x8>,
		<&apps_smmu 0xc80 0x8>;
		ranges;

		display-controller@ae01000 {
		compatible = "qcom,sdm845-dpu";
		reg = <0x0ae01000 0x8f000>,
		<0x0aeb0000 0x2008>;
		reg-names = "mdp", "vbif";

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_AXI_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK>,
		<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
		clock-names = "iface", "bus", "core", "vsync";

		interrupt-parent = <&mdss>;
		interrupts = <0>;
		power-domains = <&rpmhpd SDM845_CX>;
		operating-points-v2 = <&mdp_opp_table>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dpu_intf1_out: endpoint {
		remote-endpoint = <&dsi0_in>;
		};
		};

		port@1 {
		reg = <1>;
		dpu_intf2_out: endpoint {
		remote-endpoint = <&dsi1_in>;
		};
		};
		};
		};
		};
		...

Documentation/devicetree/bindings/display/msm/dpu.txt

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		Qualcomm Technologies, Inc. DPU KMS

		Description:

		Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
		sub-blocks like DPU display controller, DSI and DP interfaces etc.
		The DPU display controller is found in SDM845 SoC.

		MDSS:
		Required properties:
		- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
		- reg: physical base address and length of controller's registers.
		- reg-names: register region names. The following region is required:
		* "mdss"
		- power-domains: a power domain consumer specifier according to
		Documentation/devicetree/bindings/power/power_domain.txt
		- clocks: list of clock specifiers for clocks needed by the device.
		- clock-names: device clock names, must be in same order as clocks property.
		The following clocks are required:
		* "iface"
		* "bus"
		* "core"
		- interrupts: interrupt signal from MDSS.
		- interrupt-controller: identifies the node as an interrupt controller.
		- #interrupt-cells: specifies the number of cells needed to encode an interrupt
		source, should be 1.
		- iommus: phandle of iommu device node.
		- #address-cells: number of address cells for the MDSS children. Should be 1.
		- #size-cells: Should be 1.
		- ranges: parent bus address space is the same as the child bus address space.
		- interconnects : interconnect path specifier for MDSS according to
		Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
		2 paths corresponding to 2 AXI ports.
		- interconnect-names : MDSS will have 2 port names to differentiate between the
		2 interconnect paths defined with interconnect specifier.

		Optional properties:
		- assigned-clocks: list of clock specifiers for clocks needing rate assignment
		- assigned-clock-rates: list of clock frequencies sorted in the same order as
		the assigned-clocks property.

		MDP:
		Required properties:
		- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
		- reg: physical base address and length of controller's registers.
		- reg-names : register region names. The following region is required:
		* "mdp"
		* "vbif"
		- clocks: list of clock specifiers for clocks needed by the device.
		- clock-names: device clock names, must be in same order as clocks property.
		The following clocks are required.
		* "bus"
		* "iface"
		* "core"
		* "vsync"
		- interrupts: interrupt line from DPU to MDSS.
		- ports: contains the list of output ports from DPU device. These ports connect
		to interfaces that are external to the DPU hardware, such as DSI, DP etc.

		Each output port contains an endpoint that describes how it is connected to an
		external interface. These are described by the standard properties documented
		here:
		Documentation/devicetree/bindings/graph.txt
		Documentation/devicetree/bindings/media/video-interfaces.txt

		Port 0 -> DPU_INTF1 (DSI1)
		Port 1 -> DPU_INTF2 (DSI2)

		Optional properties:
		- assigned-clocks: list of clock specifiers for clocks needing rate assignment
		- assigned-clock-rates: list of clock frequencies sorted in the same order as
		the assigned-clocks property.

		Example:

		mdss: mdss@ae00000 {
		compatible = "qcom,sdm845-mdss";
		reg = <0xae00000 0x1000>;
		reg-names = "mdss";

		power-domains = <&clock_dispcc 0>;

		clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
		<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
		clock-names = "iface", "bus", "core";

		assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
		assigned-clock-rates = <300000000>;

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;

		interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
		<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;

		interconnect-names = "mdp0-mem", "mdp1-mem";

		iommus = <&apps_iommu 0>;

		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0xae00000 0xb2008>;

		mdss_mdp: mdp@ae01000 {
		compatible = "qcom,sdm845-dpu";
		reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
		reg-names = "mdp", "vbif";

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
		<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
		<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
		<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
		clock-names = "iface", "bus", "core", "vsync";

		assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
		<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
		assigned-clock-rates = <0 0 300000000 19200000>;

		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dpu_intf1_out: endpoint {
		remote-endpoint = <&dsi0_in>;
		};
		};

		port@1 {
		reg = <1>;
		dpu_intf2_out: endpoint {
		remote-endpoint = <&dsi1_in>;
		};
		};
		};
		};
		};