Commit 3d590056 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v5.11-tag1' of... 

Merge tag 'renesas-pinctrl-for-v5.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.11

  - Add remaining video-in (VIN) pin groups on R-Car H2 and RZ/G1H,
  - Image size optimizations and code consolidations,
  - Minor fixes and improvements.
parents 3603a537 d4aac7d4

drivers/pinctrl/renesas/core.c

+2 −0
Original line number Diff line number Diff line
@@ -315,6 +315,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 
		range = NULL;

		break;



#ifdef CONFIG_PINCTRL_SH_PFC_GPIO

	case PINMUX_TYPE_OUTPUT:

		range = &pfc->info->output;

		break;
@@ -322,6 +323,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 
	case PINMUX_TYPE_INPUT:

		range = &pfc->info->input;

		break;

#endif /* CONFIG_PINCTRL_SH_PFC_GPIO */



	default:

		return -EINVAL;

drivers/pinctrl/renesas/core.h

+4 −0
Original line number Diff line number Diff line
@@ -33,4 +33,8 @@ const struct pinmux_bias_reg * 
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,

		       unsigned int *bit);



unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);

void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,

			  unsigned int bias);



#endif /* __SH_PFC_CORE_H__ */

drivers/pinctrl/renesas/gpio.c

+1 −1
Original line number Diff line number Diff line
@@ -328,7 +328,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) 
	if (pfc->info->data_regs == NULL)

		return 0;



	/* Find the memory window that contain the GPIO registers. Boards that

	/* Find the memory window that contains the GPIO registers. Boards that

	 * register a separate GPIO device will not supply a memory resource

	 * that covers the data registers. In that case don't try to handle

	 * GPIOs.

drivers/pinctrl/renesas/pfc-r8a7778.c

+8 −47
Original line number Diff line number Diff line
@@ -2909,7 +2909,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
};



static const struct pinmux_bias_reg pinmux_bias_regs[] = {

	{ PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {

	{ PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) {

		[ 0] = RCAR_GP_PIN(0,  6),	/* A0 */

		[ 1] = RCAR_GP_PIN(0,  7),	/* A1 */

		[ 2] = RCAR_GP_PIN(0,  8),	/* A2 */
@@ -2943,7 +2943,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { 
		[30] = RCAR_GP_PIN(1,  7),	/* /EX_CS4 */

		[31] = RCAR_GP_PIN(1,  8),	/* /EX_CS5 */

	} },

	{ PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {

	{ PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) {

		[ 0] = RCAR_GP_PIN(0,  0),	/* /PRESETOUT	*/

		[ 1] = RCAR_GP_PIN(0,  5),	/* /BS		*/

		[ 2] = RCAR_GP_PIN(1,  0),	/* RD//WR	*/
@@ -2977,7 +2977,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { 
		[30] = SH_PFC_PIN_NONE,

		[31] = SH_PFC_PIN_NONE,

	} },

	{ PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {

	{ PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) {

		[ 0] = RCAR_GP_PIN(1, 22),	/* DU0_DR0	*/

		[ 1] = RCAR_GP_PIN(1, 23),	/* DU0_DR1	*/

		[ 2] = RCAR_GP_PIN(1, 24),	/* DU0_DR2	*/
@@ -3011,7 +3011,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { 
		[30] = RCAR_GP_PIN(2, 21),	/* DU0_CDE	*/

		[31] = RCAR_GP_PIN(2, 16),	/* DU0_DOTCLKOUT1 */

	} },

	{ PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {

	{ PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) {

		[ 0] = RCAR_GP_PIN(3, 24),	/* VI0_CLK	*/

		[ 1] = RCAR_GP_PIN(3, 25),	/* VI0_CLKENB	*/

		[ 2] = RCAR_GP_PIN(3, 26),	/* VI0_FIELD	*/
@@ -3045,7 +3045,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { 
		[30] = RCAR_GP_PIN(4, 18),	/* ETH_MDIO	*/

		[31] = RCAR_GP_PIN(4, 19),	/* ETH_LINK	*/

	} },

	{ PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {

	{ PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) {

		[ 0] = RCAR_GP_PIN(3,  6),	/* SSI_SCK012	*/

		[ 1] = RCAR_GP_PIN(3,  7),	/* SSI_WS012	*/

		[ 2] = RCAR_GP_PIN(3, 10),	/* SSI_SDATA0	*/
@@ -3079,7 +3079,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { 
		[30] = RCAR_GP_PIN(1, 14),	/* IRQ2		*/

		[31] = RCAR_GP_PIN(1, 15),	/* IRQ3		*/

	} },

	{ PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {

	{ PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) {

		[ 0] = RCAR_GP_PIN(0,  1),	/* PENC0	*/

		[ 1] = RCAR_GP_PIN(0,  2),	/* PENC1	*/

		[ 2] = RCAR_GP_PIN(0,  3),	/* USB_OVC0	*/
@@ -3116,48 +3116,9 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { 
	{ /* sentinel */ },

};



static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,

					    unsigned int pin)

{

	const struct pinmux_bias_reg *reg;

	void __iomem *addr;

	unsigned int bit;



	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);

	if (!reg)

		return PIN_CONFIG_BIAS_DISABLE;



	addr = pfc->windows->virt + reg->puen;



	if (ioread32(addr) & BIT(bit))

		return PIN_CONFIG_BIAS_PULL_UP;

	else

		return PIN_CONFIG_BIAS_DISABLE;

}



static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,

				   unsigned int bias)

{

	const struct pinmux_bias_reg *reg;

	void __iomem *addr;

	unsigned int bit;

	u32 value;



	reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);

	if (!reg)

		return;



	addr = pfc->windows->virt + reg->puen;



	value = ioread32(addr) & ~BIT(bit);

	if (bias == PIN_CONFIG_BIAS_PULL_UP)

		value |= BIT(bit);

	iowrite32(value, addr);

}



static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {

	.get_bias = r8a7778_pinmux_get_bias,

	.set_bias = r8a7778_pinmux_set_bias,

	.get_bias = rcar_pinmux_get_bias,

	.set_bias = rcar_pinmux_set_bias,

};



const struct sh_pfc_soc_info r8a7778_pinmux_info = {

drivers/pinctrl/renesas/pfc-r8a7790.c

+145 −1
Original line number Diff line number Diff line
@@ -2393,6 +2393,8 @@ static const unsigned int intc_irq3_pins[] = { 
static const unsigned int intc_irq3_mux[] = {

	IRQ3_MARK,

};



#ifdef CONFIG_PINCTRL_PFC_R8A7790

/* - MLB+ ------------------------------------------------------------------- */

static const unsigned int mlb_3pin_pins[] = {

	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
@@ -2400,6 +2402,8 @@ static const unsigned int mlb_3pin_pins[] = { 
static const unsigned int mlb_3pin_mux[] = {

	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,

};

#endif /* CONFIG_PINCTRL_PFC_R8A7790 */



/* - MMCIF0 ----------------------------------------------------------------- */

static const unsigned int mmc0_data1_pins[] = {

	/* D[0] */
@@ -3866,6 +3870,72 @@ static const unsigned int vin1_data18_mux[] = { 
	VI1_R4_MARK, VI1_R5_MARK,

	VI1_R6_MARK, VI1_R7_MARK,

};

static const union vin_data vin1_data_b_pins = {

	.data24 = {

		/* B */

		RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),

		RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),

		RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),

		RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),

		/* G */

		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),

		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),

		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),

		RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),

		/* R */

		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),

		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),

		RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),

		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),

	},

};

static const union vin_data vin1_data_b_mux = {

	.data24 = {

		/* B */

		VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,

		VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,

		VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,

		VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,

		/* G */

		VI1_G0_B_MARK, VI1_G1_B_MARK,

		VI1_G2_B_MARK, VI1_G3_B_MARK,

		VI1_G4_B_MARK, VI1_G5_B_MARK,

		VI1_G6_B_MARK, VI1_G7_B_MARK,

		/* R */

		VI1_R0_B_MARK, VI1_R1_B_MARK,

		VI1_R2_B_MARK, VI1_R3_B_MARK,

		VI1_R4_B_MARK, VI1_R5_B_MARK,

		VI1_R6_B_MARK, VI1_R7_B_MARK,

	},

};

static const unsigned int vin1_data18_b_pins[] = {

	/* B */

	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),

	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),

	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),

	/* G */

	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),

	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),

	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),

	/* R */

	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),

	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),

	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),

};

static const unsigned int vin1_data18_b_mux[] = {

	/* B */

	VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,

	VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,

	VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,

	/* G */

	VI1_G2_B_MARK, VI1_G3_B_MARK,

	VI1_G4_B_MARK, VI1_G5_B_MARK,

	VI1_G6_B_MARK, VI1_G7_B_MARK,

	/* R */

	VI1_R2_B_MARK, VI1_R3_B_MARK,

	VI1_R4_B_MARK, VI1_R5_B_MARK,

	VI1_R6_B_MARK, VI1_R7_B_MARK,

};

static const unsigned int vin1_sync_pins[] = {

	RCAR_GP_PIN(1, 24), /* HSYNC */

	RCAR_GP_PIN(1, 25), /* VSYNC */
@@ -3874,24 +3944,50 @@ static const unsigned int vin1_sync_mux[] = { 
	VI1_HSYNC_N_MARK,

	VI1_VSYNC_N_MARK,

};

static const unsigned int vin1_sync_b_pins[] = {

	RCAR_GP_PIN(1, 24), /* HSYNC */

	RCAR_GP_PIN(1, 25), /* VSYNC */

};

static const unsigned int vin1_sync_b_mux[] = {

	VI1_HSYNC_N_B_MARK,

	VI1_VSYNC_N_B_MARK,

};

static const unsigned int vin1_field_pins[] = {

	RCAR_GP_PIN(1, 13),

};

static const unsigned int vin1_field_mux[] = {

	VI1_FIELD_MARK,

};

static const unsigned int vin1_field_b_pins[] = {

	RCAR_GP_PIN(1, 13),

};

static const unsigned int vin1_field_b_mux[] = {

	VI1_FIELD_B_MARK,

};

static const unsigned int vin1_clkenb_pins[] = {

	RCAR_GP_PIN(1, 26),

};

static const unsigned int vin1_clkenb_mux[] = {

	VI1_CLKENB_MARK,

};

static const unsigned int vin1_clkenb_b_pins[] = {

	RCAR_GP_PIN(1, 26),

};

static const unsigned int vin1_clkenb_b_mux[] = {

	VI1_CLKENB_B_MARK,

};

static const unsigned int vin1_clk_pins[] = {

	RCAR_GP_PIN(2, 9),

};

static const unsigned int vin1_clk_mux[] = {

	VI1_CLK_MARK,

};

static const unsigned int vin1_clk_b_pins[] = {

	RCAR_GP_PIN(3, 15),

};

static const unsigned int vin1_clk_b_mux[] = {

	VI1_CLK_B_MARK,

};

/* - VIN2 ----------------------------------------------------------------- */

static const union vin_data vin2_data_pins = {

	.data24 = {
@@ -3959,6 +4055,18 @@ static const unsigned int vin2_data18_mux[] = { 
	VI2_R4_MARK, VI2_R5_MARK,

	VI2_R6_MARK, VI2_R7_MARK,

};

static const unsigned int vin2_g8_pins[] = {

	RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),

	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),

	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),

	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),

};

static const unsigned int vin2_g8_mux[] = {

	VI2_G0_MARK, VI2_G1_MARK,

	VI2_G2_MARK, VI2_G3_MARK,

	VI2_G4_MARK, VI2_G5_MARK,

	VI2_G6_MARK, VI2_G7_MARK,

};

static const unsigned int vin2_sync_pins[] = {

	RCAR_GP_PIN(1, 16), /* HSYNC */

	RCAR_GP_PIN(1, 21), /* VSYNC */
@@ -4026,8 +4134,10 @@ static const unsigned int vin3_clk_mux[] = { 
};



static const struct {

	struct sh_pfc_pin_group common[298];

	struct sh_pfc_pin_group common[311];

#ifdef CONFIG_PINCTRL_PFC_R8A7790

	struct sh_pfc_pin_group automotive[1];

#endif

} pinmux_groups = {

	.common = {

		SH_PFC_PIN_GROUP(audio_clk_a),
@@ -4310,15 +4420,28 @@ static const struct { 
		VIN_DATA_PIN_GROUP(vin1_data, 10),

		VIN_DATA_PIN_GROUP(vin1_data, 8),

		VIN_DATA_PIN_GROUP(vin1_data, 4),

		VIN_DATA_PIN_GROUP(vin1_data, 24, _b),

		VIN_DATA_PIN_GROUP(vin1_data, 20, _b),

		SH_PFC_PIN_GROUP(vin1_data18_b),

		VIN_DATA_PIN_GROUP(vin1_data, 16, _b),

		VIN_DATA_PIN_GROUP(vin1_data, 12, _b),

		VIN_DATA_PIN_GROUP(vin1_data, 10, _b),

		VIN_DATA_PIN_GROUP(vin1_data, 8, _b),

		VIN_DATA_PIN_GROUP(vin1_data, 4, _b),

		SH_PFC_PIN_GROUP(vin1_sync),

		SH_PFC_PIN_GROUP(vin1_sync_b),

		SH_PFC_PIN_GROUP(vin1_field),

		SH_PFC_PIN_GROUP(vin1_field_b),

		SH_PFC_PIN_GROUP(vin1_clkenb),

		SH_PFC_PIN_GROUP(vin1_clkenb_b),

		SH_PFC_PIN_GROUP(vin1_clk),

		SH_PFC_PIN_GROUP(vin1_clk_b),

		VIN_DATA_PIN_GROUP(vin2_data, 24),

		SH_PFC_PIN_GROUP(vin2_data18),

		VIN_DATA_PIN_GROUP(vin2_data, 16),

		VIN_DATA_PIN_GROUP(vin2_data, 8),

		VIN_DATA_PIN_GROUP(vin2_data, 4),

		SH_PFC_PIN_GROUP(vin2_g8),

		SH_PFC_PIN_GROUP(vin2_sync),

		SH_PFC_PIN_GROUP(vin2_field),

		SH_PFC_PIN_GROUP(vin2_clkenb),
@@ -4329,9 +4452,11 @@ static const struct { 
		SH_PFC_PIN_GROUP(vin3_clkenb),

		SH_PFC_PIN_GROUP(vin3_clk),

	},

#ifdef CONFIG_PINCTRL_PFC_R8A7790

	.automotive = {

		SH_PFC_PIN_GROUP(mlb_3pin),

	}

#endif /* CONFIG_PINCTRL_PFC_R8A7790 */

};



static const char * const audio_clk_groups[] = {
@@ -4475,9 +4600,11 @@ static const char * const intc_groups[] = { 
	"intc_irq3",

};



#ifdef CONFIG_PINCTRL_PFC_R8A7790

static const char * const mlb_groups[] = {

	"mlb_3pin",

};

#endif /* CONFIG_PINCTRL_PFC_R8A7790 */



static const char * const mmc0_groups[] = {

	"mmc0_data1",
@@ -4784,10 +4911,22 @@ static const char * const vin1_groups[] = { 
	"vin1_data10",

	"vin1_data8",

	"vin1_data4",

	"vin1_data24_b",

	"vin1_data20_b",

	"vin1_data18_b",

	"vin1_data16_b",

	"vin1_data12_b",

	"vin1_data10_b",

	"vin1_data8_b",

	"vin1_data4_b",

	"vin1_sync",

	"vin1_sync_b",

	"vin1_field",

	"vin1_field_b",

	"vin1_clkenb",

	"vin1_clkenb_b",

	"vin1_clk",

	"vin1_clk_b",

};



static const char * const vin2_groups[] = {
@@ -4796,6 +4935,7 @@ static const char * const vin2_groups[] = { 
	"vin2_data16",

	"vin2_data8",

	"vin2_data4",

	"vin2_g8",

	"vin2_sync",

	"vin2_field",

	"vin2_clkenb",
@@ -4812,7 +4952,9 @@ static const char * const vin3_groups[] = { 


static const struct {

	struct sh_pfc_function common[58];

#ifdef CONFIG_PINCTRL_PFC_R8A7790

	struct sh_pfc_function automotive[1];

#endif

} pinmux_functions = {

	.common = {

		SH_PFC_FUNCTION(audio_clk),
@@ -4874,9 +5016,11 @@ static const struct { 
		SH_PFC_FUNCTION(vin2),

		SH_PFC_FUNCTION(vin3),

	},

#ifdef CONFIG_PINCTRL_PFC_R8A7790

	.automotive = {

		SH_PFC_FUNCTION(mlb),

	}

#endif /* CONFIG_PINCTRL_PFC_R8A7790 */

};



static const struct pinmux_cfg_reg pinmux_config_regs[] = {