Commit 3d274f8b authored by Marek Vasut's avatar Marek Vasut Committed by Shawn Guo
Browse files

arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM 



The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent f4662e0c

arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts

+2 −0
Original line number Diff line number Diff line
@@ -105,7 +105,9 @@ 
};



&fec {	/* Second ethernet */

	pinctrl-0 = <&pinctrl_fec_rgmii>;

	phy-handle = <&ethphypdk>;

	phy-mode = "rgmii";



	mdio {

		ethphypdk: ethernet-phy@7 { /* KSZ 9021 */

arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi

+19 −3
Original line number Diff line number Diff line
@@ -129,9 +129,9 @@ 


&fec {	/* Second ethernet */

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec>;

	pinctrl-0 = <&pinctrl_fec_rmii>;

	phy-handle = <&ethphy1f>;

	phy-mode = "rgmii";

	phy-mode = "rmii";

	fsl,magic-packet;

	status = "okay";
@@ -732,7 +732,7 @@ 
		>;

	};



	pinctrl_fec: dhcom-fec-grp {

	pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {	/* RGMII */

		fsl,pins = <

			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x1f

			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
@@ -753,6 +753,22 @@ 
		>;

	};



	pinctrl_fec_rmii: dhcom-fec-rmii-grp {	/* RMII */

		fsl,pins = <

			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3

			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3

			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91

			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91

			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91

			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x91

			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f

			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f

			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f

			/* Clock */

			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x4000001f

		>;

	};



	pinctrl_flexcan1: dhcom-flexcan1-grp {

		fsl,pins = <

			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154