Unverified Commit 3d1486ef authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!9753 v2 arm64: arm_pmuv3: Correctly extract and check the PMUVer 

Merge Pull Request from: @ci-robot 
 
PR sync from: Junhao He <hejunhao3@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/GGLHD4NZY2QAR4OGERIIRAS2V53JQHRS/ 
 
https://gitee.com/openeuler/kernel/issues/I9J01A 
 
Link:https://gitee.com/openeuler/kernel/pulls/9753

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents d2d5c86a 5cfa9c7f

arch/arm64/include/asm/assembler.h

+4 −3
Original line number Diff line number Diff line
@@ -466,9 +466,10 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU 
 */

	.macro	reset_pmuserenr_el0, tmpreg

	mrs	\tmpreg, id_aa64dfr0_el1

	sbfx	\tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4

	cmp	\tmpreg, #1			// Skip if no PMU present

	b.lt	9000f

	ubfx	\tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4

	cmp     \tmpreg, #ID_AA64DFR0_PMUVER_NI

	ccmp    \tmpreg, #ID_AA64DFR0_PMUVER_IMP_DEF, #4, ne

	b.eq	9000f

	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0

9000:

	.endm

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -1488,6 +1488,7 @@ 
#define ID_AA64DFR0_EL1_BRBE_NI		0x0

#define ID_AA64DFR0_EL1_BRBE_IMP	0x1

#define ID_AA64DFR0_EL1_BRBE_BRBE_V1P1	0x2

#define ID_AA64DFR0_PMUVER_NI		0x0

#define ID_AA64DFR0_PMUVER_8_0		0x1

#define ID_AA64DFR0_PMUVER_8_1		0x4

#define ID_AA64DFR0_PMUVER_8_4		0x5

arch/arm64/kernel/head.S

+5 −4
Original line number Diff line number Diff line
@@ -623,13 +623,14 @@ set_hcr: 


	/* EL2 debug */

	mrs	x1, id_aa64dfr0_el1

	sbfx	x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4

	cmp	x0, #1

	b.lt	4f				// Skip if no PMU present

	ubfx	x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4

	cmp	x0, #ID_AA64DFR0_PMUVER_NI

	ccmp	x0, #ID_AA64DFR0_PMUVER_IMP_DEF, #4, ne

	b.eq	4f				// Skip if no PMU present

	mrs	x0, pmcr_el0			// Disable debug access traps

	ubfx	x0, x0, #11, #5			// to EL2 and allow access to

4:

	csel	x3, xzr, x0, lt			// all PMU counters from EL1

	csel	x3, xzr, x0, eq			// all PMU counters from EL1



	/* Statistical profiling */

	ubfx	x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4