Commit 3cf377ee authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: fulfill SMU13.0.7 cstate control interface 



Fulfill the functionality for cstate control.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x
parent c6863be2

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

+12 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = 
	MSG_MAP(Mode1Reset,             PPSMC_MSG_Mode1Reset,                  0),

	MSG_MAP(PrepareMp1ForUnload,		PPSMC_MSG_PrepareMp1ForUnload,         0),

	MSG_MAP(SetMGpuFanBoostLimitRpm,	PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),

	MSG_MAP(DFCstateControl,		PPSMC_MSG_SetExternalClientDfCstateAllow, 0),

};



static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
@@ -1587,6 +1588,16 @@ static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu) 


	return true;

}



static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,

				     enum pp_df_cstate state)

{

	return smu_cmn_send_smc_msg_with_param(smu,

					       SMU_MSG_DFCstateControl,

					       state,

					       NULL);

}



static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {

	.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,

	.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -1649,6 +1660,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { 
	.mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,

	.mode1_reset = smu_v13_0_mode1_reset,

	.set_mp1_state = smu_v13_0_7_set_mp1_state,

	.set_df_cstate = smu_v13_0_7_set_df_cstate,

};



void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)