Commit 3cc30140 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v5.19-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull pci updates from Bjorn Helgaas:
 "Resource management:

   - Restrict E820 clipping to PCI host bridge windows (Bjorn Helgaas)

   - Log E820 clipping better (Bjorn Helgaas)

   - Add kernel cmdline options to enable/disable E820 clipping (Hans de
     Goede)

   - Disable E820 reserved region clipping for IdeaPads, Yoga, Yoga
     Slip, Acer Spin 5, Clevo Barebone systems where clipping leaves no
     usable address space for touchpads, Thunderbolt devices, etc (Hans
     de Goede)

   - Disable E820 clipping by default starting in 2023 (Hans de Goede)

  PCI device hotplug:

   - Include files to remove implicit dependencies (Christophe Leroy)

   - Only put Root Ports in D3 if they can signal and wake from D3 so
     AMD Yellow Carp doesn't miss hotplug events (Mario Limonciello)

  Power management:

   - Define pci_restore_standard_config() only for CONFIG_PM_SLEEP since
     it's unused otherwise (Krzysztof Kozlowski)

   - Power up devices completely, including anything platform firmware
     needs to do, during runtime resume (Rafael J. Wysocki)

   - Move pci_resume_bus() to PM callbacks so we observe the required
     bridge power-up delays (Rafael J. Wysocki)

   - Drop unneeded runtime_d3cold device flag (Rafael J. Wysocki)

   - Split pci_raw_set_power_state() between pci_power_up() and a new
     pci_set_low_power_state() (Rafael J. Wysocki)

   - Set current_state to D3cold if config read returns ~0, indicating
     the device is not accessible (Rafael J. Wysocki)

   - Do not call pci_update_current_state() from pci_power_up() so BARs
     and ASPM config are restored correctly (Rafael J. Wysocki)

   - Write 0 to PMCSR in pci_power_up() in all cases (Rafael J. Wysocki)

   - Split pci_power_up() to pci_set_full_power_state() to avoid some
     redundant operations (Rafael J. Wysocki)

   - Skip restoring BARs if device is not in D0 (Rafael J. Wysocki)

   - Rearrange and clarify pci_set_power_state() (Rafael J. Wysocki)

   - Remove redundant BAR restores from pci_pm_thaw_noirq() (Rafael J.
     Wysocki)

  Virtualization:

   - Acquire device lock before config space access lock to avoid AB/BA
     deadlock with sriov_numvfs_store() (Yicong Yang)

  Error handling:

   - Clear MULTI_ERR_COR/UNCOR_RCV bits, which a race could previously
     leave permanently set (Kuppuswamy Sathyanarayanan)

  Peer-to-peer DMA:

   - Whitelist Intel Skylake-E Root Ports regardless of which devfn they
     are (Shlomo Pongratz)

  ASPM:

   - Override L1 acceptable latency advertised by Intel DG2 so ASPM L1
     can be enabled (Mika Westerberg)

  Cadence PCIe controller driver:

   - Set up device-specific register to allow PTM Responder to be
     enabled by the normal architected bit (Christian Gmeiner)

   - Override advertised FLR support since the controller doesn't
     implement FLR correctly (Parshuram Thombare)

  Cadence PCIe endpoint driver:

   - Correct bitmap size for the ob_region_map of outbound window usage
     (Dan Carpenter)

  Freescale i.MX6 PCIe controller driver:

   - Fix PERST# assertion/deassertion so we observe the required delays
     before accessing device (Francesco Dolcini)

  Freescale Layerscape PCIe controller driver:

   - Add "big-endian" DT property (Hou Zhiqiang)

   - Update SCFG DT property (Hou Zhiqiang)

   - Add "aer", "pme", "intr" DT properties (Li Yang)

   - Add DT compatible strings for ls1028a (Xiaowei Bao)

  Intel VMD host bridge driver:

   - Assign VMD IRQ domain before enumeration to avoid IOMMU interrupt
     remapping errors when MSI-X remapping is disabled (Nirmal Patel)

   - Revert VMD workaround that kept MSI-X remapping enabled when IOMMU
     remapping was enabled (Nirmal Patel)

  Marvell MVEBU PCIe controller driver:

   - Add of_pci_get_slot_power_limit() to parse the
     'slot-power-limit-milliwatt' DT property (Pali Rohár)

   - Add mvebu support for sending Set_Slot_Power_Limit message (Pali
     Rohár)

  MediaTek PCIe controller driver:

   - Fix refcount leak in mtk_pcie_subsys_powerup() (Miaoqian Lin)

  MediaTek PCIe Gen3 controller driver:

   - Reset PHY and MAC at probe time (AngeloGioacchino Del Regno)

  Microchip PolarFlare PCIe controller driver:

   - Add chained_irq_enter()/chained_irq_exit() calls to mc_handle_msi()
     and mc_handle_intx() to avoid lost interrupts (Conor Dooley)

   - Fix interrupt handling race (Daire McNamara)

  NVIDIA Tegra194 PCIe controller driver:

   - Drop tegra194 MSI register save/restore, which is unnecessary since
     the DWC core does it (Jisheng Zhang)

  Qualcomm PCIe controller driver:

   - Add SM8150 SoC DT binding and support (Bhupesh Sharma)

   - Fix pipe clock imbalance (Johan Hovold)

   - Fix runtime PM imbalance on probe errors (Johan Hovold)

   - Fix PHY init imbalance on probe errors (Johan Hovold)

   - Convert DT binding to YAML (Dmitry Baryshkov)

   - Update DT binding to show that resets aren't required for
     MSM8996/APQ8096 platforms (Dmitry Baryshkov)

   - Add explicit register names per chipset in DT binding (Dmitry
     Baryshkov)

   - Add sc7280-specific clock and reset definitions to DT binding
     (Dmitry Baryshkov)

  Rockchip PCIe controller driver:

   - Fix bitmap size when searching for free outbound region (Dan
     Carpenter)

  Rockchip DesignWare PCIe controller driver:

   - Remove "snps,dw-pcie" from rockchip-dwc DT "compatible" property
     because it's not fully compatible with rockchip (Peter Geis)

   - Reset rockchip-dwc controller at probe (Peter Geis)

   - Add rockchip-dwc INTx support (Peter Geis)

  Synopsys DesignWare PCIe controller driver:

   - Return error instead of success if DMA mapping of MSI area fails
     (Jiantao Zhang)

  Miscellaneous:

   - Change pci_set_dma_mask() documentation references to
     dma_set_mask() (Alex Williamson)"

* tag 'pci-v5.19-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (64 commits)
  dt-bindings: PCI: qcom: Add schema for sc7280 chipset
  dt-bindings: PCI: qcom: Specify reg-names explicitly
  dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms
  dt-bindings: PCI: qcom: Convert to YAML
  PCI: qcom: Fix unbalanced PHY init on probe errors
  PCI: qcom: Fix runtime PM imbalance on probe errors
  PCI: qcom: Fix pipe clock imbalance
  PCI: qcom: Add SM8150 SoC support
  dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC
  x86/PCI: Disable E820 reserved region clipping starting in 2023
  x86/PCI: Disable E820 reserved region clipping via quirks
  x86/PCI: Add kernel cmdline options to use/ignore E820 reserved regions
  PCI: microchip: Fix potential race in interrupt handling
  PCI/AER: Clear MULTI_ERR_COR/UNCOR_RCV bits
  PCI: cadence: Clear FLR in device capabilities register
  PCI: cadence: Allow PTM Responder to be enabled
  PCI: vmd: Revert 2565e5b6 ("PCI: vmd: Do not disable MSI-X remapping if interrupt remapping is enabled by IOMMU.")
  PCI: vmd: Assign VMD IRQ domain before enumeration
  PCI: Avoid pci_dev_lock() AB/BA deadlock with sriov_numvfs_store()
  PCI: rockchip-dwc: Add legacy interrupt support
  ...
parents 8291eaaf 32f479d0

Documentation/PCI/pci.rst

+2 −2
Original line number Diff line number Diff line
@@ -273,12 +273,12 @@ Set the DMA mask size 
While all drivers should explicitly indicate the DMA capability

(e.g. 32 or 64 bit) of the PCI bus master, devices with more than

32-bit bus master capability for streaming data need the driver

to "register" this capability by calling pci_set_dma_mask() with

to "register" this capability by calling dma_set_mask() with

appropriate parameters.  In general this allows more efficient DMA

on systems where System RAM exists above 4G _physical_ address.



Drivers for all PCI-X and PCIe compliant devices must call

set_dma_mask() as they are 64-bit DMA devices.

dma_set_mask() as they are 64-bit DMA devices.



Similarly, drivers must also "register" this capability if the device

can directly address "coherent memory" in System RAM above 4G physical

Documentation/admin-guide/kernel-parameters.txt

+9 −0
Original line number Diff line number Diff line
@@ -4099,6 +4099,15 @@ 
				please report a bug.

		nocrs		[X86] Ignore PCI host bridge windows from ACPI.

				If you need to use this, please report a bug.

		use_e820	[X86] Use E820 reservations to exclude parts of

				PCI host bridge windows. This is a workaround

				for BIOS defects in host bridge _CRS methods.

				If you need to use this, please report a bug to

				<linux-pci@vger.kernel.org>.

		no_e820		[X86] Ignore E820 reservations for PCI host

				bridge windows. This is the default on modern

				hardware. If you need to use this, please report

				a bug to <linux-pci@vger.kernel.org>.

		routeirq	Do IRQ routing for all PCI devices.

				This is normally done in pci_enable_device(),

				so this option is a temporary workaround

Documentation/devicetree/bindings/pci/layerscape-pci.txt

+38 −27
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ Required properties: 
        "fsl,ls1012a-pcie"

        "fsl,ls1028a-pcie"

  EP mode:

	"fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"

	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"

	"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"

	"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
@@ -30,39 +31,49 @@ Required properties: 
- reg: base addresses and lengths of the PCIe controller register blocks.

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: Must include the following entries:

  "intr": The interrupt that is asserted for controller interrupts

- interrupt-names: It could include the following entries:

  "aer": Used for interrupt line which reports AER events when

	 non MSI/MSI-X/INTx mode is used

  "pme": Used for interrupt line which reports PME events when

	 non MSI/MSI-X/INTx mode is used

  "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)

	  which has a single interrupt line for miscellaneous controller

	  events(could include AER and PME events).

- fsl,pcie-scfg: Must include two entries.

  The first entry must be a link to the SCFG device node

  The second entry must be '0' or '1' based on physical PCIe controller index.

  The second entry is the physical PCIe controller index starting from '0'.

  This is used to get SCFG PEXN registers

- dma-coherent: Indicates that the hardware IP block can ensure the coherency

  of the data transferred from/to the IP block. This can avoid the software

  cache flush/invalid actions, and improve the performance significantly.



Optional properties:

- big-endian: If the PEX_LUT and PF register block is in big-endian, specify

  this property.



Example:



        pcie@3400000 {

		compatible = "fsl,ls1021a-pcie";

		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */

		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */

                compatible = "fsl,ls1088a-pcie";

                reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */

                      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */

                reg-names = "regs", "config";

		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */

		interrupt-names = "intr";

		fsl,pcie-scfg = <&scfg 0>;

                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */

                interrupt-names = "aer";

                #address-cells = <3>;

                #size-cells = <2>;

                device_type = "pci";

                dma-coherent;

		num-lanes = <4>;

                num-viewport = <256>;

                bus-range = <0x0 0xff>;

		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

			  0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000   /* prefetchable memory */

			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

                ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */

                          0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

                msi-parent = <&its>;

                #interrupt-cells = <1>;

                interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;

                interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,

                                <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,

                                <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,

                                <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;

                iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */

        };

Documentation/devicetree/bindings/pci/qcom,pcie.txt

deleted100644 → 0
+0 −397
Original line number Diff line number Diff line 
* Qualcomm PCI express root complex



- compatible:

	Usage: required

	Value type: <stringlist>

	Definition: Value should contain

			- "qcom,pcie-ipq8064" for ipq8064

			- "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065

			- "qcom,pcie-apq8064" for apq8064

			- "qcom,pcie-apq8084" for apq8084

			- "qcom,pcie-msm8996" for msm8996 or apq8096

			- "qcom,pcie-ipq4019" for ipq4019

			- "qcom,pcie-ipq8074" for ipq8074

			- "qcom,pcie-qcs404" for qcs404

			- "qcom,pcie-sc8180x" for sc8180x

			- "qcom,pcie-sdm845" for sdm845

			- "qcom,pcie-sm8250" for sm8250

			- "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450

			- "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450

			- "qcom,pcie-ipq6018" for ipq6018



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Register ranges as listed in the reg-names property



- reg-names:

	Usage: required

	Value type: <stringlist>

	Definition: Must include the following entries

			- "parf"   Qualcomm specific registers

			- "dbi"	   DesignWare PCIe registers

			- "elbi"   External local bus interface registers

			- "config" PCIe configuration space

			- "atu"    ATU address space (optional)



- device_type:

	Usage: required

	Value type: <string>

	Definition: Should be "pci". As specified in snps,dw-pcie.yaml



- #address-cells:

	Usage: required

	Value type: <u32>

	Definition: Should be 3. As specified in snps,dw-pcie.yaml



- #size-cells:

	Usage: required

	Value type: <u32>

	Definition: Should be 2. As specified in snps,dw-pcie.yaml



- ranges:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: As specified in snps,dw-pcie.yaml



- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: MSI interrupt



- interrupt-names:

	Usage: required

	Value type: <stringlist>

	Definition: Should contain "msi"



- #interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: Should be 1. As specified in snps,dw-pcie.yaml



- interrupt-map-mask:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: As specified in snps,dw-pcie.yaml



- interrupt-map:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: As specified in snps,dw-pcie.yaml



- clocks:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: List of phandle and clock specifier pairs as listed

		    in clock-names property



- clock-names:

	Usage: required

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "iface"	Configuration AHB clock



- clock-names:

	Usage: required for ipq/apq8064

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "core"	Clocks the pcie hw block

			- "phy"		Clocks the pcie PHY block

			- "aux" 	Clocks the pcie AUX block

			- "ref" 	Clocks the pcie ref block

- clock-names:

	Usage: required for apq8084/ipq4019

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"		Auxiliary (AUX) clock

			- "bus_master"	Master AXI clock

			- "bus_slave"	Slave AXI clock



- clock-names:

	Usage: required for msm8996/apq8096

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "pipe"	Pipe Clock driving internal logic

			- "aux"		Auxiliary (AUX) clock

			- "cfg"		Configuration clock

			- "bus_master"	Master AXI clock

			- "bus_slave"	Slave AXI clock



- clock-names:

	Usage: required for ipq8074

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "iface"	PCIe to SysNOC BIU clock

			- "axi_m"	AXI Master clock

			- "axi_s"	AXI Slave clock

			- "ahb"		AHB clock

			- "aux"		Auxiliary clock



- clock-names:

	Usage: required for ipq6018

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "iface"	PCIe to SysNOC BIU clock

			- "axi_m"	AXI Master clock

			- "axi_s"	AXI Slave clock

			- "axi_bridge"	AXI bridge clock

			- "rchng"



- clock-names:

	Usage: required for qcs404

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "iface"	AHB clock

			- "aux"		Auxiliary clock

			- "master_bus"	AXI Master clock

			- "slave_bus"	AXI Slave clock



- clock-names:

	Usage: required for sdm845

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"		Auxiliary clock

			- "cfg"		Configuration clock

			- "bus_master"	Master AXI clock

			- "bus_slave"	Slave AXI clock

			- "slave_q2a"	Slave Q2A clock

			- "tbu"		PCIe TBU clock

			- "pipe"	PIPE clock



- clock-names:

	Usage: required for sc8180x and sm8250

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"		Auxiliary clock

			- "cfg"		Configuration clock

			- "bus_master"	Master AXI clock

			- "bus_slave"	Slave AXI clock

			- "slave_q2a"	Slave Q2A clock

			- "tbu"		PCIe TBU clock

			- "ddrss_sf_tbu" PCIe SF TBU clock

			- "pipe"	PIPE clock



- clock-names:

	Usage: required for sm8450-pcie0 and sm8450-pcie1

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"         Auxiliary clock

			- "cfg"         Configuration clock

			- "bus_master"  Master AXI clock

			- "bus_slave"   Slave AXI clock

			- "slave_q2a"   Slave Q2A clock

			- "tbu"         PCIe TBU clock

			- "ddrss_sf_tbu" PCIe SF TBU clock

			- "pipe"        PIPE clock

			- "pipe_mux"    PIPE MUX

			- "phy_pipe"    PIPE output clock

			- "ref"         REFERENCE clock

			- "aggre0"	Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0

			- "aggre1"	Aggre NoC PCIe1 AXI clock



- resets:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: List of phandle and reset specifier pairs as listed

		    in reset-names property



- reset-names:

	Usage: required for ipq/apq8064

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "axi"  AXI reset

			- "ahb"  AHB reset

			- "por"  POR reset

			- "pci"  PCI reset

			- "phy"  PHY reset



- reset-names:

	Usage: required for apq8084

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "core" Core reset



- reset-names:

	Usage: required for ipq/apq8064

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "axi_m"		AXI master reset

			- "axi_s"		AXI slave reset

			- "pipe"		PIPE reset

			- "axi_m_vmid"		VMID reset

			- "axi_s_xpu"		XPU reset

			- "parf"		PARF reset

			- "phy"			PHY reset

			- "axi_m_sticky"	AXI sticky reset

			- "pipe_sticky"		PIPE sticky reset

			- "pwr"			PWR reset

			- "ahb"			AHB reset

			- "phy_ahb"		PHY AHB reset

			- "ext"			EXT reset



- reset-names:

	Usage: required for ipq8074

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "pipe"		PIPE reset

			- "sleep"		Sleep reset

			- "sticky"		Core Sticky reset

			- "axi_m"		AXI Master reset

			- "axi_s"		AXI Slave reset

			- "ahb"			AHB Reset

			- "axi_m_sticky"	AXI Master Sticky reset



- reset-names:

	Usage: required for ipq6018

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "pipe"		PIPE reset

			- "sleep"		Sleep reset

			- "sticky"		Core Sticky reset

			- "axi_m"		AXI Master reset

			- "axi_s"		AXI Slave reset

			- "ahb"			AHB Reset

			- "axi_m_sticky"	AXI Master Sticky reset

			- "axi_s_sticky"	AXI Slave Sticky reset



- reset-names:

	Usage: required for qcs404

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "axi_m"		AXI Master reset

			- "axi_s"		AXI Slave reset

			- "axi_m_sticky"	AXI Master Sticky reset

			- "pipe_sticky"		PIPE sticky reset

			- "pwr"			PWR reset

			- "ahb"			AHB reset



- reset-names:

	Usage: required for sc8180x, sdm845, sm8250 and sm8450

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "pci"			PCIe core reset



- power-domains:

	Usage: required for apq8084 and msm8996/apq8096

	Value type: <prop-encoded-array>

	Definition: A phandle and power domain specifier pair to the

		    power domain which is responsible for collapsing

		    and restoring power to the peripheral



- vdda-supply:

	Usage: required

	Value type: <phandle>

	Definition: A phandle to the core analog power supply



- vdda_phy-supply:

	Usage: required for ipq/apq8064

	Value type: <phandle>

	Definition: A phandle to the analog power supply for PHY



- vdda_refclk-supply:

	Usage: required for ipq/apq8064

	Value type: <phandle>

	Definition: A phandle to the analog power supply for IC which generates

		    reference clock

- vddpe-3v3-supply:

	Usage: optional

	Value type: <phandle>

	Definition: A phandle to the PCIe endpoint power supply



- phys:

	Usage: required for apq8084 and qcs404

	Value type: <phandle>

	Definition: List of phandle(s) as listed in phy-names property



- phy-names:

	Usage: required for apq8084 and qcs404

	Value type: <stringlist>

	Definition: Should contain "pciephy"



- <name>-gpios:

	Usage: optional

	Value type: <prop-encoded-array>

	Definition: List of phandle and GPIO specifier pairs. Should contain

			- "perst-gpios"	PCIe endpoint reset signal line

			- "wake-gpios"	PCIe endpoint wake signal line



* Example for ipq/apq8064

	pcie@1b500000 {

		compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";

		reg = <0x1b500000 0x1000

		       0x1b502000 0x80

		       0x1b600000 0x100

		       0x0ff00000 0x100000>;

		reg-names = "dbi", "elbi", "parf", "config";

		device_type = "pci";

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		num-lanes = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */

			  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */

		interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

				<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

				<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

				<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

		clocks = <&gcc PCIE_A_CLK>,

			 <&gcc PCIE_H_CLK>,

			 <&gcc PCIE_PHY_CLK>,

			 <&gcc PCIE_AUX_CLK>,

			 <&gcc PCIE_ALT_REF_CLK>;

		clock-names = "core", "iface", "phy", "aux", "ref";

		resets = <&gcc PCIE_ACLK_RESET>,

			 <&gcc PCIE_HCLK_RESET>,

			 <&gcc PCIE_POR_RESET>,

			 <&gcc PCIE_PCI_RESET>,

			 <&gcc PCIE_PHY_RESET>,

			 <&gcc PCIE_EXT_RESET>;

		reset-names = "axi", "ahb", "por", "pci", "phy", "ext";

		pinctrl-0 = <&pcie_pins_default>;

		pinctrl-names = "default";

	};



* Example for apq8084

	pcie0@fc520000 {

		compatible = "qcom,pcie-apq8084", "snps,dw-pcie";

		reg = <0xfc520000 0x2000>,

		      <0xff000000 0x1000>,

		      <0xff001000 0x1000>,

		      <0xff002000 0x2000>;

		reg-names = "parf", "dbi", "elbi", "config";

		device_type = "pci";

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		num-lanes = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */

			  0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */

		interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

				<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

				<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

				<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

		clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,

			 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,

			 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,

			 <&gcc GCC_PCIE_0_AUX_CLK>;

		clock-names = "iface", "master_bus", "slave_bus", "aux";

		resets = <&gcc GCC_PCIE_0_BCR>;

		reset-names = "core";

		power-domains = <&gcc PCIE0_GDSC>;

		vdda-supply = <&pma8084_l3>;

		phys = <&pciephy0>;

		phy-names = "pciephy";

		perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;

		pinctrl-0 = <&pcie0_pins_default>;

		pinctrl-names = "default";

	};

Documentation/devicetree/bindings/pci/qcom,pcie.yaml

0 → 100644
+714 −0

File added.

Preview size limit exceeded, changes collapsed.