Commit 3cba4a2c authored by Akhil P Oommen's avatar Akhil P Oommen Committed by Rob Clark
Browse files

drm/msm/a6xx: Update ROQ size in coredump 



Since RoQ size differs between generations, calculate dynamically the
RoQ size while capturing coredump.

Signed-off-by: default avatarAkhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/515610/
Link: https://lore.kernel.org/r/20221221203925.v2.4.I07f22966395eb045f6b312710f53890d5d7e69d4@changeid


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 1e05bba5

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

+10 −1
Original line number Diff line number Diff line
@@ -942,15 +942,24 @@ static void a6xx_get_registers(struct msm_gpu *gpu, 
			dumper);

}



static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)

{

	/* The value at [16:31] is in 4dword units. Convert it to dwords */

	return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14;

}



/* Read a block of data from an indexed register pair */

static void a6xx_get_indexed_regs(struct msm_gpu *gpu,

		struct a6xx_gpu_state *a6xx_state,

		const struct a6xx_indexed_registers *indexed,

		struct a6xx_indexed_registers *indexed,

		struct a6xx_gpu_state_obj *obj)

{

	int i;



	obj->handle = (const void *) indexed;

	if (indexed->count_fn)

		indexed->count = indexed->count_fn(gpu);



	obj->data = state_kcalloc(a6xx_state, indexed->count, sizeof(u32));

	if (!obj->data)

		return;

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+10 −7
Original line number Diff line number Diff line
@@ -383,25 +383,28 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = { 
	REGS(a6xx_gmu_gx_registers, 0, 0),

};



static const struct a6xx_indexed_registers {

static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);



static struct a6xx_indexed_registers {

	const char *name;

	u32 addr;

	u32 data;

	u32 count;

	u32 (*count_fn)(struct msm_gpu *gpu);

} a6xx_indexed_reglist[] = {

	{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,

		REG_A6XX_CP_SQE_STAT_DATA, 0x33 },

		REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },

	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,

		REG_A6XX_CP_DRAW_STATE_DATA, 0x100 },

		REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },

	{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,

		REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x6000 },

		REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },

	{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,

		REG_A6XX_CP_ROQ_DBG_DATA, 0x400 },

		REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},

};



static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {

static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {

	"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,

		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060,

		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,

};



#define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }