Commit 3ca40237 authored by Wyatt Wood's avatar Wyatt Wood Committed by Alex Deucher
Browse files

drm/amd/display: Refactor and add visual confirm for HW Flip Queue 



[Why]
Visual confirm will indicate if driver is programming
the surface address.
Refactor is required because much of the visual confirm
logic is buried deep in the mpcc files.
In addition, visual confirm is not updated during fast updates.

[How]
In order to have visual confirm for driver flips, visual confirm
needs to be updated on every frame, including fast updates.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.

v2: drop unused variable (Alex)

Signed-off-by: default avatarWyatt Wood <wyatt.wood@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 60d177fd

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+19 −13
Original line number Diff line number Diff line
@@ -2502,9 +2502,25 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state 
		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

}



void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)

{

	struct dce_hwseq *hws = dc->hwseq;

	struct mpc *mpc = dc->res_pool->mpc;



	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)

		hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, color);

	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

		hws->funcs.get_surface_visual_confirm_color(pipe_ctx, color);

	else

		color_space_to_black_color(

				dc, pipe_ctx->stream->output_color_space, color);



	if (mpc->funcs->set_bg_color)

		mpc->funcs->set_bg_color(mpc, color, mpcc_id);

}



void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

{

	struct hubp *hubp = pipe_ctx->plane_res.hubp;

	struct mpcc_blnd_cfg blnd_cfg = {{0}};

	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
@@ -2513,18 +2529,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 
	struct mpc *mpc = dc->res_pool->mpc;

	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);



	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {

		hws->funcs.get_hdr_visual_confirm_color(

				pipe_ctx, &blnd_cfg.black_color);

	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {

		hws->funcs.get_surface_visual_confirm_color(

				pipe_ctx, &blnd_cfg.black_color);

	} else {

		color_space_to_black_color(

				dc, pipe_ctx->stream->output_color_space,

				&blnd_cfg.black_color);

	}



	if (per_pixel_alpha)

		blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;

	else
@@ -2556,6 +2560,8 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 
	 */

	mpcc_id = hubp->inst;



	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);



	/* If there is no full update, don't need to touch MPC tree*/

	if (!pipe_ctx->plane_state->update_flags.bits.full_update) {

		mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

+6 −0
Original line number Diff line number Diff line
@@ -206,4 +206,10 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc); 


void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);



void dcn10_update_visual_confirm_color(

		struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		struct tg_color *color,

		int mpcc_id);



#endif /* __DC_HWSS_DCN10_H__ */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c

+1 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { 
	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,

	.set_pipe = dce110_set_pipe,

	.get_dcc_en_bits = dcn10_get_dcc_en_bits,

	.update_visual_confirm_color = dcn10_update_visual_confirm_color,

};



static const struct hwseq_private_funcs dcn10_private_funcs = {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c

+5 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ void mpc1_set_bg_color(struct mpc *mpc, 
			MPCC_BG_G_Y, bg_g_y);

	REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,

			MPCC_BG_B_CB, bg_b_cb);



	bottommost_mpcc->blnd_cfg.black_color = *bg_color;

}



static void mpc1_update_blending(
@@ -246,6 +248,8 @@ struct mpcc *mpc1_insert_plane( 
		}

	}



	mpc->funcs->set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);



	/* update the blending configuration */

	mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
@@ -495,6 +499,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = { 
	.set_output_csc = NULL,

	.set_output_gamma = NULL,

	.get_mpc_out_mux = mpc1_get_mpc_out_mux,

	.set_bg_color = mpc1_set_bg_color,

};



void dcn10_mpc_construct(struct dcn10_mpc *mpc10,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+19 −10
Original line number Diff line number Diff line
@@ -2267,9 +2267,25 @@ void dcn20_get_mpctree_visual_confirm_color( 
	*color = pipe_colors[top_pipe->pipe_idx];

}



void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)

{

	struct dce_hwseq *hws = dc->hwseq;

	struct mpc *mpc = dc->res_pool->mpc;



	/* input to MPCC is always RGB, by default leave black_color at 0 */

	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)

		hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, color);

	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)

		hws->funcs.get_surface_visual_confirm_color(pipe_ctx, color);

	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)

		dcn20_get_mpctree_visual_confirm_color(pipe_ctx, color);



	if (mpc->funcs->set_bg_color)

		mpc->funcs->set_bg_color(mpc, color, mpcc_id);

}



void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

{

	struct hubp *hubp = pipe_ctx->plane_res.hubp;

	struct mpcc_blnd_cfg blnd_cfg = { {0} };

	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
@@ -2278,15 +2294,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 
	struct mpc *mpc = dc->res_pool->mpc;

	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);



	// input to MPCC is always RGB, by default leave black_color at 0

	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {

		hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);

	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {

		hws->funcs.get_surface_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);

	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {

		dcn20_get_mpctree_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);

	}



	if (per_pixel_alpha)

		blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;

	else
@@ -2320,6 +2327,8 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 
	 */

	mpcc_id = hubp->inst;



	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);



	/* If there is no full update, don't need to touch MPC tree*/

	if (!pipe_ctx->plane_state->update_flags.bits.full_update &&

		!pipe_ctx->update_flags.bits.mpcc) {