Commit 3c938cc5 authored by Schspa Shi's avatar Schspa Shi Committed by Bartosz Golaszewski
Browse files

gpio: use raw spinlock for gpio chip shadowed data 



In case of PREEMPT_RT, there is a raw_spinlock -> spinlock dependency
as the lockdep report shows.

__irq_set_handler
  irq_get_desc_buslock
    __irq_get_desc_lock
      raw_spin_lock_irqsave(&desc->lock, *flags);  // raw spinlock get here
  __irq_do_set_handler
    mask_ack_irq
      dwapb_irq_ack
        spin_lock_irqsave(&gc->bgpio_lock, flags); // sleep able spinlock
  irq_put_desc_busunlock

Replace with a raw lock to avoid BUGs. This lock is only used to access
registers, and It's safe to replace with the raw lock without bad
influence.

[   15.090359][    T1] =============================
[   15.090365][    T1] [ BUG: Invalid wait context ]
[   15.090373][    T1] 5.10.59-rt52-00983-g186a6841c682-dirty #3 Not tainted
[   15.090386][    T1] -----------------------------
[   15.090392][    T1] swapper/0/1 is trying to lock:
[   15.090402][    T1] 70ff00018507c188 (&gc->bgpio_lock){....}-{3:3}, at: _raw_spin_lock_irqsave+0x1c/0x28
[   15.090470][    T1] other info that might help us debug this:
[   15.090477][    T1] context-{5:5}
[   15.090485][    T1] 3 locks held by swapper/0/1:
[   15.090497][    T1]  #0: c2ff0001816de1a0 (&dev->mutex){....}-{4:4}, at: __device_driver_lock+0x98/0x104
[   15.090553][    T1]  #1: ffff90001485b4b8 (irq_domain_mutex){+.+.}-{4:4}, at: irq_domain_associate+0xbc/0x6d4
[   15.090606][    T1]  #2: 4bff000185d7a8e0 (lock_class){....}-{2:2}, at: _raw_spin_lock_irqsave+0x1c/0x28
[   15.090654][    T1] stack backtrace:
[   15.090661][    T1] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.10.59-rt52-00983-g186a6841c682-dirty #3
[   15.090682][    T1] Hardware name: Horizon Robotics Journey 5 DVB (DT)
[   15.090692][    T1] Call trace:
......
[   15.090811][    T1]  _raw_spin_lock_irqsave+0x1c/0x28
[   15.090828][    T1]  dwapb_irq_ack+0xb4/0x300
[   15.090846][    T1]  __irq_do_set_handler+0x494/0xb2c
[   15.090864][    T1]  __irq_set_handler+0x74/0x114
[   15.090881][    T1]  irq_set_chip_and_handler_name+0x44/0x58
[   15.090900][    T1]  gpiochip_irq_map+0x210/0x644

Signed-off-by: default avatarSchspa Shi <schspa@gmail.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarDoug Berger <opendmb@gmail.com>
Acked-by: default avatarSerge Semin <fancer.lancer@gmail.com>
Signed-off-by: default avatarBartosz Golaszewski <brgl@bgdev.pl>
parent 4f3e79b3

drivers/gpio/gpio-amdpt.c

+5 −5
Original line number Diff line number Diff line
@@ -36,19 +36,19 @@ static int pt_gpio_request(struct gpio_chip *gc, unsigned offset) 


	dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset);



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);



	using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);

	if (using_pins & BIT(offset)) {

		dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n",

			 offset);

		spin_unlock_irqrestore(&gc->bgpio_lock, flags);

		raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);

		return -EINVAL;

	}



	writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG);



	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);



	return 0;

}
@@ -59,13 +59,13 @@ static void pt_gpio_free(struct gpio_chip *gc, unsigned offset) 
	unsigned long flags;

	u32 using_pins;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);



	using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);

	using_pins &= ~BIT(offset);

	writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG);



	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);



	dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset);

}

drivers/gpio/gpio-brcmstb.c

+6 −6
Original line number Diff line number Diff line
@@ -92,9 +92,9 @@ brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) 
	unsigned long status;

	unsigned long flags;



	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);

	raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);

	status = __brcmstb_gpio_get_active_irqs(bank);

	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);



	return status;

}
@@ -114,14 +114,14 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, 
	u32 imask;

	unsigned long flags;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));

	if (enable)

		imask |= mask;

	else

		imask &= ~mask;

	gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);

}



static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
@@ -204,7 +204,7 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
		return -EINVAL;

	}



	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);

	raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);



	iedge_config = bank->gc.read_reg(priv->reg_base +

			GIO_EC(bank->id)) & ~mask;
@@ -220,7 +220,7 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
	bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),

			ilevel | level);



	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);

	return 0;

}

drivers/gpio/gpio-cadence.c

+6 −6
Original line number Diff line number Diff line
@@ -41,12 +41,12 @@ static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset) 
	struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);

	unsigned long flags;



	spin_lock_irqsave(&chip->bgpio_lock, flags);

	raw_spin_lock_irqsave(&chip->bgpio_lock, flags);



	iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),

		  cgpio->regs + CDNS_GPIO_BYPASS_MODE);



	spin_unlock_irqrestore(&chip->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);

	return 0;

}
@@ -55,13 +55,13 @@ static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset) 
	struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);

	unsigned long flags;



	spin_lock_irqsave(&chip->bgpio_lock, flags);

	raw_spin_lock_irqsave(&chip->bgpio_lock, flags);



	iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |

		  (BIT(offset) & cgpio->bypass_orig),

		  cgpio->regs + CDNS_GPIO_BYPASS_MODE);



	spin_unlock_irqrestore(&chip->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);

}



static void cdns_gpio_irq_mask(struct irq_data *d)
@@ -90,7 +90,7 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
	u32 mask = BIT(d->hwirq);

	int ret = 0;



	spin_lock_irqsave(&chip->bgpio_lock, flags);

	raw_spin_lock_irqsave(&chip->bgpio_lock, flags);



	int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;

	int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
@@ -115,7 +115,7 @@ static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
	iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);



err_irq_type:

	spin_unlock_irqrestore(&chip->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags);

	return ret;

}

drivers/gpio/gpio-dwapb.c

+18 −18
Original line number Diff line number Diff line
@@ -243,9 +243,9 @@ static void dwapb_irq_ack(struct irq_data *d) 
	u32 val = BIT(irqd_to_hwirq(d));

	unsigned long flags;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	dwapb_write(gpio, GPIO_PORTA_EOI, val);

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);

}



static void dwapb_irq_mask(struct irq_data *d)
@@ -255,10 +255,10 @@ static void dwapb_irq_mask(struct irq_data *d) 
	unsigned long flags;

	u32 val;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));

	dwapb_write(gpio, GPIO_INTMASK, val);

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);

}



static void dwapb_irq_unmask(struct irq_data *d)
@@ -268,10 +268,10 @@ static void dwapb_irq_unmask(struct irq_data *d) 
	unsigned long flags;

	u32 val;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));

	dwapb_write(gpio, GPIO_INTMASK, val);

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);

}



static void dwapb_irq_enable(struct irq_data *d)
@@ -281,11 +281,11 @@ static void dwapb_irq_enable(struct irq_data *d) 
	unsigned long flags;

	u32 val;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	val = dwapb_read(gpio, GPIO_INTEN);

	val |= BIT(irqd_to_hwirq(d));

	dwapb_write(gpio, GPIO_INTEN, val);

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);

}



static void dwapb_irq_disable(struct irq_data *d)
@@ -295,11 +295,11 @@ static void dwapb_irq_disable(struct irq_data *d) 
	unsigned long flags;

	u32 val;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	val = dwapb_read(gpio, GPIO_INTEN);

	val &= ~BIT(irqd_to_hwirq(d));

	dwapb_write(gpio, GPIO_INTEN, val);

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);

}



static int dwapb_irq_set_type(struct irq_data *d, u32 type)
@@ -309,7 +309,7 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type) 
	irq_hw_number_t bit = irqd_to_hwirq(d);

	unsigned long level, polarity, flags;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);

	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
@@ -344,7 +344,7 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type) 
	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);

	if (type != IRQ_TYPE_EDGE_BOTH)

		dwapb_write(gpio, GPIO_INT_POLARITY, polarity);

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);



	return 0;

}
@@ -374,7 +374,7 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc, 
	unsigned long flags, val_deb;

	unsigned long mask = BIT(offset);



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);



	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);

	if (debounce)
@@ -383,7 +383,7 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc, 
		val_deb &= ~mask;

	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);



	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);



	return 0;

}
@@ -738,7 +738,7 @@ static int dwapb_gpio_suspend(struct device *dev) 
	unsigned long flags;

	int i;



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	for (i = 0; i < gpio->nr_ports; i++) {

		unsigned int offset;

		unsigned int idx = gpio->ports[i].idx;
@@ -765,7 +765,7 @@ static int dwapb_gpio_suspend(struct device *dev) 
			dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);

		}

	}

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);



	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
@@ -785,7 +785,7 @@ static int dwapb_gpio_resume(struct device *dev) 
		return err;

	}



	spin_lock_irqsave(&gc->bgpio_lock, flags);

	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);

	for (i = 0; i < gpio->nr_ports; i++) {

		unsigned int offset;

		unsigned int idx = gpio->ports[i].idx;
@@ -812,7 +812,7 @@ static int dwapb_gpio_resume(struct device *dev) 
			dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);

		}

	}

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);



	return 0;

}

drivers/gpio/gpio-grgpio.c

+15 −15
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ static int grgpio_irq_set_type(struct irq_data *d, unsigned int type) 
		return -EINVAL;

	}



	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);



	ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;

	iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
@@ -153,7 +153,7 @@ static int grgpio_irq_set_type(struct irq_data *d, unsigned int type) 
	priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);

	priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);



	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);



	return 0;

}
@@ -164,11 +164,11 @@ static void grgpio_irq_mask(struct irq_data *d) 
	int offset = d->hwirq;

	unsigned long flags;



	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);



	grgpio_set_imask(priv, offset, 0);



	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

}



static void grgpio_irq_unmask(struct irq_data *d)
@@ -177,11 +177,11 @@ static void grgpio_irq_unmask(struct irq_data *d) 
	int offset = d->hwirq;

	unsigned long flags;



	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);



	grgpio_set_imask(priv, offset, 1);



	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

}



static struct irq_chip grgpio_irq_chip = {
@@ -199,7 +199,7 @@ static irqreturn_t grgpio_irq_handler(int irq, void *dev) 
	int i;

	int match = 0;



	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);



	/*

	 * For each gpio line, call its interrupt handler if it its underlying
@@ -215,7 +215,7 @@ static irqreturn_t grgpio_irq_handler(int irq, void *dev) 
		}

	}



	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);



	if (!match)

		dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
@@ -247,13 +247,13 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq, 
	dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",

		irq, offset);



	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);



	/* Request underlying irq if not already requested */

	lirq->irq = irq;

	uirq = &priv->uirqs[lirq->index];

	if (uirq->refcnt == 0) {

		spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

		raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

		ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,

				  dev_name(priv->dev), priv);

		if (ret) {
@@ -262,11 +262,11 @@ static int grgpio_irq_map(struct irq_domain *d, unsigned int irq, 
				uirq->uirq);

			return ret;

		}

		spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

		raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	}

	uirq->refcnt++;



	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);



	/* Setup irq  */

	irq_set_chip_data(irq, priv);
@@ -290,7 +290,7 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq) 
	irq_set_chip_and_handler(irq, NULL, NULL);

	irq_set_chip_data(irq, NULL);



	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);

	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);



	/* Free underlying irq if last user unmapped */

	index = -1;
@@ -309,13 +309,13 @@ static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq) 
		uirq = &priv->uirqs[lirq->index];

		uirq->refcnt--;

		if (uirq->refcnt == 0) {

			spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

			raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

			free_irq(uirq->uirq, priv);

			return;

		}

	}



	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);

}



static const struct irq_domain_ops grgpio_irq_domain_ops = {