Commit 3c91d7e8 authored by Vadim Pasternak's avatar Vadim Pasternak Committed by Hans de Goede
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platform: mellanox: mlx-platform: Fix signals polarity and latch mask 



Change polarity of chassis health and power signals and fix latch reset
mask for L1 switch.

Fixes: dd635e33 ("platform: mellanox: Introduce support of new Nvidia L1 switch")
Signed-off-by: default avatarVadim Pasternak <vadimp@nvidia.com>
Reviewed-by: default avatarMichael Shych <michaelsh@nvidia.com>
Link: https://lore.kernel.org/r/20230813083735.39090-3-vadimp@nvidia.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 8e3938cf

drivers/platform/x86/mlx-platform.c

+4 −4
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ 
#define MLXPLAT_CPLD_GWP_MASK		GENMASK(0, 0)

#define MLXPLAT_CPLD_EROT_MASK		GENMASK(1, 0)

#define MLXPLAT_CPLD_PWR_BUTTON_MASK	BIT(0)

#define MLXPLAT_CPLD_LATCH_RST_MASK	BIT(5)

#define MLXPLAT_CPLD_LATCH_RST_MASK	BIT(6)

#define MLXPLAT_CPLD_THERMAL1_PDB_MASK	BIT(3)

#define MLXPLAT_CPLD_THERMAL2_PDB_MASK	BIT(4)

#define MLXPLAT_CPLD_INTRUSION_MASK	BIT(6)
@@ -2475,7 +2475,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { 
		.reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET,

		.mask = MLXPLAT_CPLD_PWR_BUTTON_MASK,

		.count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data),

		.inversed = 0,

		.inversed = 1,

		.health = false,

	},

	{
@@ -2484,7 +2484,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { 
		.reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,

		.mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK,

		.count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data),

		.inversed = 0,

		.inversed = 1,

		.health = false,

		.ind = 8,

	},
@@ -3677,7 +3677,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 
	{

		.label = "latch_reset",

		.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,

		.mask = GENMASK(7, 0) & ~BIT(5),

		.mask = GENMASK(7, 0) & ~BIT(6),

		.mode = 0200,

	},

	{