Commit 3c816d95 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

ARM: pxa: move clk register definitions to driver 



The clock register definitions are now used (almost) exclusively in the
clk driver, and that relies on no other mach/*.h header files any more.

Remove the dependency on mach/pxa*-regs.h by addressing the registers
as offsets from a void __iomem * pointer, which is either passed from
a board file, or (for the moment) ioremapped at boot time from a hardcoded
address in case of DT (this should be moved into the DT of course).

Cc: linux-clk@vger.kernel.org
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Acked-by: default avatarRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent fd13f811

arch/arm/mach-pxa/generic.c

+4 −3
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include <linux/init.h>

#include <linux/soc/pxa/cpu.h>

#include <linux/soc/pxa/smemc.h>

#include <linux/clk/pxa.h>



#include <asm/mach/map.h>

#include <asm/mach-types.h>
@@ -48,11 +49,11 @@ void clear_reset_status(unsigned int mask) 
void __init pxa_timer_init(void)

{

	if (cpu_is_pxa25x())

		pxa25x_clocks_init();

		pxa25x_clocks_init(io_p2v(0x41300000));

	if (cpu_is_pxa27x())

		pxa27x_clocks_init();

		pxa27x_clocks_init(io_p2v(0x41300000));

	if (cpu_is_pxa3xx())

		pxa3xx_clocks_init();

		pxa3xx_clocks_init(io_p2v(0x41340000), io_p2v(0x41350000));

	pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000));

}

arch/arm/mach-pxa/generic.h

+0 −3
Original line number Diff line number Diff line
@@ -22,19 +22,16 @@ extern void pxa_timer_init(void); 
#define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)



#define pxa25x_handle_irq icip_handle_irq

extern int __init pxa25x_clocks_init(void);

extern void __init pxa25x_init_irq(void);

extern void __init pxa25x_map_io(void);

extern void __init pxa26x_init_irq(void);



#define pxa27x_handle_irq ichp_handle_irq

extern int __init pxa27x_clocks_init(void);

extern unsigned	pxa27x_get_clk_frequency_khz(int);

extern void __init pxa27x_init_irq(void);

extern void __init pxa27x_map_io(void);



#define pxa3xx_handle_irq ichp_handle_irq

extern int __init pxa3xx_clocks_init(void);

extern void __init pxa3xx_init_irq(void);

extern void __init pxa3xx_map_io(void);

arch/arm/mach-pxa/include/mach/pxa2xx-regs.h

+0 −45
Original line number Diff line number Diff line
@@ -136,51 +136,6 @@ 
#define CKEN		io_p2v(0x41300004)  /* Clock Enable Register */

#define OSCC		io_p2v(0x41300008)  /* Oscillator Configuration Register */



#define CCCR_N_MASK	0x0380	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */

#define CCCR_M_MASK	0x0060	/* Memory Frequency to Run Mode Frequency Multiplier */

#define CCCR_L_MASK	0x001f	/* Crystal Frequency to Memory Frequency Multiplier */



#define CCCR_CPDIS_BIT	(31)

#define CCCR_PPDIS_BIT	(30)

#define CCCR_LCD_26_BIT	(27)

#define CCCR_A_BIT	(25)



#define CCSR_N2_MASK	CCCR_N_MASK

#define CCSR_M_MASK	CCCR_M_MASK

#define CCSR_L_MASK	CCCR_L_MASK

#define CCSR_N2_SHIFT	7



#define CKEN_AC97CONF   (31)    /* AC97 Controller Configuration */

#define CKEN_CAMERA	(24)	/* Camera Interface Clock Enable */

#define CKEN_SSP1	(23)	/* SSP1 Unit Clock Enable */

#define CKEN_MEMC	(22)	/* Memory Controller Clock Enable */

#define CKEN_MEMSTK	(21)	/* Memory Stick Host Controller */

#define CKEN_IM		(20)	/* Internal Memory Clock Enable */

#define CKEN_KEYPAD	(19)	/* Keypad Interface Clock Enable */

#define CKEN_USIM	(18)	/* USIM Unit Clock Enable */

#define CKEN_MSL	(17)	/* MSL Unit Clock Enable */

#define CKEN_LCD	(16)	/* LCD Unit Clock Enable */

#define CKEN_PWRI2C	(15)	/* PWR I2C Unit Clock Enable */

#define CKEN_I2C	(14)	/* I2C Unit Clock Enable */

#define CKEN_FICP	(13)	/* FICP Unit Clock Enable */

#define CKEN_MMC	(12)	/* MMC Unit Clock Enable */

#define CKEN_USB	(11)	/* USB Unit Clock Enable */

#define CKEN_ASSP	(10)	/* ASSP (SSP3) Clock Enable */

#define CKEN_USBHOST	(10)	/* USB Host Unit Clock Enable */

#define CKEN_OSTIMER	(9)	/* OS Timer Unit Clock Enable */

#define CKEN_NSSP	(9)	/* NSSP (SSP2) Clock Enable */

#define CKEN_I2S	(8)	/* I2S Unit Clock Enable */

#define CKEN_BTUART	(7)	/* BTUART Unit Clock Enable */

#define CKEN_FFUART	(6)	/* FFUART Unit Clock Enable */

#define CKEN_STUART	(5)	/* STUART Unit Clock Enable */

#define CKEN_HWUART	(4)	/* HWUART Unit Clock Enable */

#define CKEN_SSP3	(4)	/* SSP3 Unit Clock Enable */

#define CKEN_SSP	(3)	/* SSP Unit Clock Enable */

#define CKEN_SSP2	(3)	/* SSP2 Unit Clock Enable */

#define CKEN_AC97	(2)	/* AC97 Unit Clock Enable */

#define CKEN_PWM1	(1)	/* PWM1 Clock Enable */

#define CKEN_PWM0	(0)	/* PWM0 Clock Enable */



#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */

#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */

arch/arm/mach-pxa/include/mach/pxa3xx-regs.h

+0 −69
Original line number Diff line number Diff line
@@ -131,73 +131,4 @@ 
#define CKENC		__REG(0x41340024)	/* C Clock Enable Register */

#define AC97_DIV	__REG(0x41340014)	/* AC97 clock divisor value register */



#define ACCR_XPDIS		(1 << 31)	/* Core PLL Output Disable */

#define ACCR_SPDIS		(1 << 30)	/* System PLL Output Disable */

#define ACCR_D0CS		(1 << 26)	/* D0 Mode Clock Select */

#define ACCR_PCCE		(1 << 11)	/* Power Mode Change Clock Enable */

#define ACCR_DDR_D0CS		(1 << 7)	/* DDR SDRAM clock frequency in D0CS (PXA31x only) */



#define ACCR_SMCFS_MASK		(0x7 << 23)	/* Static Memory Controller Frequency Select */

#define ACCR_SFLFS_MASK		(0x3 << 18)	/* Frequency Select for Internal Memory Controller */

#define ACCR_XSPCLK_MASK	(0x3 << 16)	/* Core Frequency during Frequency Change */

#define ACCR_HSS_MASK		(0x3 << 14)	/* System Bus-Clock Frequency Select */

#define ACCR_DMCFS_MASK		(0x3 << 12)	/* Dynamic Memory Controller Clock Frequency Select */

#define ACCR_XN_MASK		(0x7 << 8)	/* Core PLL Turbo-Mode-to-Run-Mode Ratio */

#define ACCR_XL_MASK		(0x1f)		/* Core PLL Run-Mode-to-Oscillator Ratio */



#define ACCR_SMCFS(x)		(((x) & 0x7) << 23)

#define ACCR_SFLFS(x)		(((x) & 0x3) << 18)

#define ACCR_XSPCLK(x)		(((x) & 0x3) << 16)

#define ACCR_HSS(x)		(((x) & 0x3) << 14)

#define ACCR_DMCFS(x)		(((x) & 0x3) << 12)

#define ACCR_XN(x)		(((x) & 0x7) << 8)

#define ACCR_XL(x)		((x) & 0x1f)



/*

 * Clock Enable Bit

 */

#define CKEN_LCD	1	/* < LCD Clock Enable */

#define CKEN_USBH	2	/* < USB host clock enable */

#define CKEN_CAMERA	3	/* < Camera interface clock enable */

#define CKEN_NAND	4	/* < NAND Flash Controller Clock Enable */

#define CKEN_USB2	6	/* < USB 2.0 client clock enable. */

#define CKEN_DMC	8	/* < Dynamic Memory Controller clock enable */

#define CKEN_SMC	9	/* < Static Memory Controller clock enable */

#define CKEN_ISC	10	/* < Internal SRAM Controller clock enable */

#define CKEN_BOOT	11	/* < Boot rom clock enable */

#define CKEN_MMC1	12	/* < MMC1 Clock enable */

#define CKEN_MMC2	13	/* < MMC2 clock enable */

#define CKEN_KEYPAD	14	/* < Keypand Controller Clock Enable */

#define CKEN_CIR	15	/* < Consumer IR Clock Enable */

#define CKEN_USIM0	17	/* < USIM[0] Clock Enable */

#define CKEN_USIM1	18	/* < USIM[1] Clock Enable */

#define CKEN_TPM	19	/* < TPM clock enable */

#define CKEN_UDC	20	/* < UDC clock enable */

#define CKEN_BTUART	21	/* < BTUART clock enable */

#define CKEN_FFUART	22	/* < FFUART clock enable */

#define CKEN_STUART	23	/* < STUART clock enable */

#define CKEN_AC97	24	/* < AC97 clock enable */

#define CKEN_TOUCH	25	/* < Touch screen Interface Clock Enable */

#define CKEN_SSP1	26	/* < SSP1 clock enable */

#define CKEN_SSP2	27	/* < SSP2 clock enable */

#define CKEN_SSP3	28	/* < SSP3 clock enable */

#define CKEN_SSP4	29	/* < SSP4 clock enable */

#define CKEN_MSL0	30	/* < MSL0 clock enable */

#define CKEN_PWM0	32	/* < PWM[0] clock enable */

#define CKEN_PWM1	33	/* < PWM[1] clock enable */

#define CKEN_I2C	36	/* < I2C clock enable */

#define CKEN_INTC	38	/* < Interrupt controller clock enable */

#define CKEN_GPIO	39	/* < GPIO clock enable */

#define CKEN_1WIRE	40	/* < 1-wire clock enable */

#define CKEN_HSIO2	41	/* < HSIO2 clock enable */

#define CKEN_MINI_IM	48	/* < Mini-IM */

#define CKEN_MINI_LCD	49	/* < Mini LCD */



#define CKEN_MMC3	5	/* < MMC3 Clock Enable */

#define CKEN_MVED	43	/* < MVED clock enable */



/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */

#define CKEN_PXA300_GCU		42	/* Graphics controller clock enable */

#define CKEN_PXA320_GCU		7	/* Graphics controller clock enable */



#endif /* __ASM_ARCH_PXA3XX_REGS_H */

arch/arm/mach-pxa/sleep.S

+3 −1
Original line number Diff line number Diff line
@@ -18,7 +18,9 @@ 


#define MDREFR_KDIV	0x200a4000	// all banks

#define CCCR_SLEEP	0x00000107	// L=7 2N=2 A=0 PPDIS=0 CPDIS=0



#define CCCR_N_MASK     0x00000380

#define CCCR_M_MASK     0x00000060

#define CCCR_L_MASK     0x0000001f

		.text



#ifdef CONFIG_PXA3xx