Unverified Commit 3c211cb7 authored by Richard Fitzgerald's avatar Richard Fitzgerald Committed by Mark Brown
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ASoC: cs42l42: Use PLL for SCLK > 12.288MHz 



It isn't possible to switch MCLK between 12MHz and 24MHz rate groups
on-the-fly - this can only be done when cs42l42 is powered-down.

All "normal" SCLK rates use an MCLK in the 12MHz group, so change the
configs for SCLK > 12.288 MHz to use the PLL to generate an MCLK in
the 12MHz group.

As this means MCLK_DIV is always 0 it can be removed from the pll
configuration setup.

Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20211015133619.4698-12-rf@opensource.cirrus.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 2a031a99

sound/soc/codecs/cs42l42.c

+18 −23
Original line number Diff line number Diff line
@@ -549,7 +549,6 @@ static const struct reg_sequence cs42l42_to_osc_seq[] = { 


struct cs42l42_pll_params {

	u32 sclk;

	u8 mclk_div;

	u8 mclk_src_sel;

	u8 sclk_prediv;

	u8 pll_div_int;
@@ -566,24 +565,24 @@ struct cs42l42_pll_params { 
 * Table 4-5 from the Datasheet

 */

static const struct cs42l42_pll_params pll_ratio_table[] = {

	{ 1411200, 0, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},

	{ 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},

	{ 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},

	{ 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},

	{ 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},

	{ 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},

	{ 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},

	{ 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},

	{ 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},

	{ 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},

	{ 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},

	{ 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},

	{ 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},

	{ 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},

	{ 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},

	{ 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0, 1},

	{ 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0, 1},

	{ 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0, 1}

	{ 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},

	{ 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},

	{ 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},

	{ 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},

	{ 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},

	{ 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},

	{ 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},

	{ 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},

	{ 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},

	{ 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},

	{ 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},

	{ 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},

	{ 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},

	{ 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},

	{ 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},

	{ 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},

	{ 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},

	{ 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}

};



static int cs42l42_pll_config(struct snd_soc_component *component)
@@ -619,10 +618,6 @@ static int cs42l42_pll_config(struct snd_soc_component *component) 
					24000000)) <<

					CS42L42_INTERNAL_FS_SHIFT);



			snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,

					CS42L42_MCLKDIV_MASK,

					(pll_ratio_table[i].mclk_div <<

					CS42L42_MCLKDIV_SHIFT));

			/* Set up the LRCLK */

			fsync = clk / cs42l42->srate;

			if (((fsync * cs42l42->srate) != clk)