Unverified Commit 3c1b4758 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
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dt-bindings: riscv: cpus: add a ref the common cpu schema 



To permit validation of RISC-V cpu nodes, "additionalProperties: true"
needs to be swapped for "unevaluatedProperties: false". To facilitate
this in a way that passes dt_binding_check, a reference to the cpu
schema is required.

Disallow the generic cache-op-block-size property that that drags in,
since the RISC-V CBO extensions do not require a common size, and have
individual properties.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230615-dubiously-parasail-79d34cefedce@spud


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent ac9a7868

Documentation/devicetree/bindings/riscv/cpus.yaml

+6 −0
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ description: | 
  two cores, each of which has two hyperthreads, could be described as

  having four harts.



allOf:

  - $ref: /schemas/cpu.yaml#



properties:

  compatible:

    oneOf:
@@ -98,6 +101,9 @@ properties: 
    $ref: "/schemas/types.yaml#/definitions/string"

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$



  # RISC-V has multiple properties for cache op block sizes as the sizes

  # differ between individual CBO extensions

  cache-op-block-size: false

  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here

  timebase-frequency: false