Commit 3bece767 authored by Haridhar Kalvala's avatar Haridhar Kalvala Committed by Radhakrishna Sripada
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drm/i915/mtl: WA to clear RDOP clock gating

parent 514b8a79
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+3 −0
Original line number Diff line number Diff line
@@ -1703,6 +1703,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
		/* Wa_18018781329 */
		wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
		wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);

		/* Wa_14015795083 */
		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
	}

	/*