Commit 3ba89b28 authored by Alexis Lothoré's avatar Alexis Lothoré Committed by Jakub Kicinski
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net: dsa: mv88e6xxx: add field to specify internal phys layout



mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)

Signed-off-by: default avatarAlexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 7a2dd00b
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+3 −1
Original line number Diff line number Diff line
@@ -465,7 +465,9 @@ static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,

static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
{
	return port < chip->info->num_internal_phys;
	return port >= chip->info->internal_phys_offset &&
		port < chip->info->num_internal_phys +
			chip->info->internal_phys_offset;
}

static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
+5 −0
Original line number Diff line number Diff line
@@ -167,6 +167,11 @@ struct mv88e6xxx_info {

	/* Supports PTP */
	bool ptp_support;

	/* Internal PHY start index. 0 means that internal PHYs range starts at
	 * port 0, 1 means internal PHYs range starts at port 1, etc
	 */
	unsigned int internal_phys_offset;
};

struct mv88e6xxx_atu_entry {
+4 −1
Original line number Diff line number Diff line
@@ -1196,9 +1196,12 @@ int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
				struct mii_bus *bus)
{
	int phy_start = chip->info->internal_phys_offset;
	int phy_end = chip->info->internal_phys_offset +
		      chip->info->num_internal_phys;
	int phy, irq;

	for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
	for (phy = phy_start; phy < phy_end; phy++) {
		irq = irq_find_mapping(chip->g2_irq.domain, phy);
		if (irq < 0)
			return irq;