Commit 3b218baa authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dinh Nguyen
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clk: socfpga: allow building N5X clocks with ARCH_N5X 



The Intel's eASIC N5X (ARCH_N5X) architecture shares a lot with Agilex
(ARCH_AGILEX) so it uses the same socfpga_agilex.dtsi, with minor
changes.  Also the clock drivers are the same.

However the clock drivers won't be build without ARCH_AGILEX.  One could
assume that ARCH_N5X simply depends on ARCH_AGILEX but this was not
modeled in Kconfig.  In current stage the ARCH_N5X is simply
unbootable.

Add a separate Kconfig entry for clocks used by both ARCH_N5X and
ARCH_AGILEX so the necessary objects will be built if either of them is
selected.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent fe07bfda

drivers/clk/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -394,6 +394,7 @@ source "drivers/clk/renesas/Kconfig" 
source "drivers/clk/rockchip/Kconfig"

source "drivers/clk/samsung/Kconfig"

source "drivers/clk/sifive/Kconfig"

source "drivers/clk/socfpga/Kconfig"

source "drivers/clk/sprd/Kconfig"

source "drivers/clk/sunxi/Kconfig"

source "drivers/clk/sunxi-ng/Kconfig"

drivers/clk/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ 
obj-$(CONFIG_CLK_SIFIVE)		+= sifive/

obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/

obj-$(CONFIG_ARCH_AGILEX)		+= socfpga/

obj-$(CONFIG_ARCH_N5X)			+= socfpga/

obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/

obj-$(CONFIG_PLAT_SPEAR)		+= spear/

obj-y					+= sprd/

drivers/clk/socfpga/Kconfig

0 → 100644
+6 −0
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# SPDX-License-Identifier: GPL-2.0

config CLK_INTEL_SOCFPGA64

	bool

	# Intel Agilex / N5X clock controller support

	default (ARCH_AGILEX || ARCH_N5X)

	depends on ARCH_AGILEX || ARCH_N5X

drivers/clk/socfpga/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -3,5 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o 
obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o

obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o

obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o

obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o

obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
 
obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-agilex.o

obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o