Commit 3b05c960 authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Matt Roper
Browse files

drm/i915/pvc: Implement w/a 16016694945 



A new PVC-specific workaround has just been added to the BSpec.

BSpec: 64027

Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220630201407.16770-1-gustavo.sousa@intel.com
parent eb1c535f

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -918,6 +918,10 @@ 
#define GEN7_L3CNTLREG1				_MMIO(0xb01c)

#define   GEN7_WA_FOR_GEN7_L3_CONTROL		0x3C47FF8C

#define   GEN7_L3AGDIS				(1 << 19)



#define XEHPC_LNCFMISCCFGREG0			_MMIO(0xb01c)

#define   XEHPC_OVRLSCCC			REG_BIT(0)



#define GEN7_L3CNTLREG2				_MMIO(0xb020)



/* MOCS (Memory Object Control State) registers */

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −0
Original line number Diff line number Diff line
@@ -2687,6 +2687,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 
		 * performance guide section.

		 */

		wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);



		/* Wa_16016694945 */

		wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);

	}



	if (IS_XEHPSDV(i915)) {