Commit 3aed240e authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Thomas Bogendoerfer
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MIPS: Loongson64: Correct TLB type for Loongson-3 Classic 



Huacai just informed me that some early Loongson-3A2000 had wrong
TLB type in Config0 register. That means we have to correct it via
PRID.

It looks like I shoudn't drop MIPS_CPU_FTLB flag in PRID case for
Loongson-3 Classic.

Fixes: da1bd297 ("MIPS: Loongson64: Probe CPU features via CPUCFG")
Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Reported-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent da1bd297

arch/mips/kernel/cpu-probe.c

+4 −1
Original line number Diff line number Diff line
@@ -1999,8 +1999,11 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 
		 * Loongson-3 Classic did not implement MIPS standard TLBINV

		 * but implemented TLBINVF and EHINV. As currently we're only

		 * using these two features, enable MIPS_CPU_TLBINV as well.

		 *

		 * Also some early Loongson-3A2000 had wrong TLB type in Config

		 * register, we correct it here.

		 */

		c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;

		c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;

		c->writecombine = _CACHE_UNCACHED_ACCELERATED;

		c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |

			MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);