Commit 3adab6c4 authored by Marc Zyngier's avatar Marc Zyngier Committed by chenxiang
Browse files

KVM: arm64: vgic-v3: Handle traps of ICV_NMIAR1_EL1 

virt inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I97WGU

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/commit/?h=arm64/nmi&id=7c7106953a9ba800f599635d514a563bb662486a



-----------------------------------------------------------

Even if we do not plan to deal with the GICv3.3 NMI feature in our
in-kernel emulation of the CPU interface for terminally broken
systems, the actual system register may still exist and raise
its ugly head.

Hit it with an UNDEF-sized hammer.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarXiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: default avatarcaijian <caijian11@h-partners.com>
parent b8c8255e

arch/arm64/kvm/hyp/vgic-v3-sr.c

+3 −0
Original line number Diff line number Diff line
@@ -1048,6 +1048,9 @@ int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu) 
			return 0;

		fn = __vgic_v3_read_iar;

		break;

	case SYS_ICC_NMIAR1_EL1:

		/* Here's an UNDEF for you */

		return 0;

	case SYS_ICC_EOIR0_EL1:

	case SYS_ICC_EOIR1_EL1:

		if (unlikely(is_read))

arch/arm64/kvm/sys_regs.c

+1 −0
Original line number Diff line number Diff line
@@ -2189,6 +2189,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	{ SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },

	{ SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },

	{ SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },

	{ SYS_DESC(SYS_ICC_NMIAR1_EL1), undef_access },

	{ SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },

	{ SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },

	{ SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },