Commit 3ad7befd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull more clk updates from Stephen Boyd:
 "This is the second batch of clk driver updates that needed a little
  more time to soak in linux-next.

   - Use modern i2c probe in vc5

   - Cleanup some includes

   - Update links to datasheets

   - Add UniPhier NX1 SoC clk support

   - Fix DT bindings for SiFive FU740

   - Revert the module platform driver support for Rockchip because it
     wasn't actually tested

   - Fix the composite clk code again as the previous fix had a one line
     bug that broke rate changes for clks that want to use the same
     parent still

   - Use the right table for a divider in ast2600 driver

   - Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because
     its critical but unused"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk
  clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites
  clk/ast2600: Fix soc revision for AHB
  clk: composite: Fix 'switching' to same clock
  clk: rockchip: drop module parts from rk3399 and rk3568 drivers
  Revert "clk: rockchip: use module_platform_driver_probe"
  clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c
  dt-bindings: clock: fu740-prci: add reset-cells
  clk: uniphier: Add SoC-glue clock source selector support for Pro4
  dt-bindings: clock: uniphier: Add clock binding for SoC-glue
  clk: uniphier: Add NX1 clock support
  dt-bindings: clock: uniphier: Add NX1 clock binding
  clk: uniphier: Add audio system and video input clock control for PXs3
  clk: si5351: Update datasheet references
  clk: vc5: Use i2c .probe_new
  clk/actions/owl-factor.c: remove superfluous headers
  clk: ingenic: Fix bugs with divided dividers
parents f44c7dbd 05cf3ec0

Documentation/devicetree/bindings/clock/sifive/fu740-prci.yaml

+4 −0
Original line number Diff line number Diff line
@@ -42,6 +42,9 @@ properties: 
  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg
@@ -57,4 +60,5 @@ examples: 
      reg = <0x10000000 0x1000>;

      clocks = <&hfclk>, <&rtcclk>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/silabs,si5351.txt

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. 


Reference

[1] Si5351A/B/C Data Sheet

    https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf

    https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf



The Si5351a/b/c are programmable i2c clock generators with up to 8 output

clocks. Si5351a also has a reduced pin-count package (MSOP10) where only

Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml

+6 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ properties: 
          - socionext,uniphier-ld11-clock

          - socionext,uniphier-ld20-clock

          - socionext,uniphier-pxs3-clock

          - socionext,uniphier-nx1-clock

      - description: Media I/O (MIO) clock, SD clock

        enum:

          - socionext,uniphier-ld4-mio-clock
@@ -33,6 +34,7 @@ properties: 
          - socionext,uniphier-ld11-mio-clock

          - socionext,uniphier-ld20-sd-clock

          - socionext,uniphier-pxs3-sd-clock

          - socionext,uniphier-nx1-sd-clock

      - description: Peripheral clock

        enum:

          - socionext,uniphier-ld4-peri-clock
@@ -43,6 +45,10 @@ properties: 
          - socionext,uniphier-ld11-peri-clock

          - socionext,uniphier-ld20-peri-clock

          - socionext,uniphier-pxs3-peri-clock

          - socionext,uniphier-nx1-peri-clock

      - description: SoC-glue clock

        enum:

          - socionext,uniphier-pro4-sg-clock



  "#clock-cells":

    const: 1

drivers/clk/actions/owl-factor.c

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 


#include <linux/clk-provider.h>

#include <linux/regmap.h>

#include <linux/slab.h>



#include "owl-factor.h"

drivers/clk/clk-ast2600.c

+7 −5
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ static DEFINE_SPINLOCK(aspeed_g6_clk_lock); 
static struct clk_hw_onecell_data *aspeed_g6_clk_data;



static void __iomem *scu_g6_base;

/* AST2600 revision: A0, A1, A2, etc */

static u8 soc_rev;



/*

 * Clocks marked with CLK_IS_CRITICAL:
@@ -191,9 +193,8 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) 
static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)

{

	unsigned int mult, div;

	u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);



	if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {

	if (soc_rev >= 2) {

		if (val & BIT(24)) {

			/* Pass through mode */

			mult = div = 1;
@@ -707,7 +708,7 @@ static const u32 ast2600_a1_axi_ahb200_tbl[] = { 
static void __init aspeed_g6_cc(struct regmap *map)

{

	struct clk_hw *hw;

	u32 val, div, divbits, chip_id, axi_div, ahb_div;

	u32 val, div, divbits, axi_div, ahb_div;



	clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
@@ -738,8 +739,7 @@ static void __init aspeed_g6_cc(struct regmap *map) 
		axi_div = 2;



	divbits = (val >> 11) & 0x3;

	regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);

	if (chip_id & BIT(16)) {

	if (soc_rev >= 1) {

		if (!divbits) {

			ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];

			if (val & BIT(16))
@@ -784,6 +784,8 @@ static void __init aspeed_g6_cc_init(struct device_node *np) 
	if (!scu_g6_base)

		return;



	soc_rev = (readl(scu_g6_base + ASPEED_G6_SILICON_REV) & CHIP_REVISION_ID) >> 16;



	aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,

				      ASPEED_G6_NUM_CLKS), GFP_KERNEL);

	if (!aspeed_g6_clk_data)