Commit 3ad2dd9c authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Rodrigo Vivi
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drm/i915/pxp: allocate a vcs context for pxp usage 



The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp initialization completion.

v2: use perma-pinned context (Chris)
v3: rename pinned_context functions (Chris)
v4: split export of pinned_context functions to a separate patch (Rodrigo)
v10: remove inclusion of intel_gt_types.h from intel_pxp.h (Jani)
v13: fixed for loop pointer dereference (Vinay)

Signed-off-by: default avatarAlan Previn <alan.previn.teres.alexis@intel.com>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210924191452.1539378-5-alan.previn.teres.alexis@intel.com
parent e6aa7136

drivers/gpu/drm/i915/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -278,6 +278,10 @@ i915-y += \ 


i915-y += i915_perf.o



# Protected execution platform (PXP) support

i915-$(CONFIG_DRM_I915_PXP) += \

	pxp/intel_pxp.o



# Post-mortem debug and GPU hang state capture

i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o

i915-$(CONFIG_DRM_I915_SELFTEST) += \

drivers/gpu/drm/i915/gt/intel_engine.h

+2 −0
Original line number Diff line number Diff line
@@ -175,6 +175,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) 
#define I915_GEM_HWS_SEQNO		0x40

#define I915_GEM_HWS_SEQNO_ADDR		(I915_GEM_HWS_SEQNO * sizeof(u32))

#define I915_GEM_HWS_MIGRATE		(0x42 * sizeof(u32))

#define I915_GEM_HWS_PXP		0x60

#define I915_GEM_HWS_PXP_ADDR		(I915_GEM_HWS_PXP * sizeof(u32))

#define I915_GEM_HWS_SCRATCH		0x80



#define I915_HWS_CSB_BUF0_INDEX		0x10

drivers/gpu/drm/i915/gt/intel_gt.c

+5 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include "intel_rps.h"

#include "intel_uncore.h"

#include "shmem_utils.h"

#include "pxp/intel_pxp.h"



void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)

{
@@ -714,6 +715,8 @@ int intel_gt_init(struct intel_gt *gt) 


	intel_migrate_init(&gt->migrate, gt);



	intel_pxp_init(&gt->pxp);



	goto out_fw;

err_gt:

	__intel_gt_disable(gt);
@@ -751,6 +754,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt) 


	intel_rps_driver_unregister(&gt->rps);



	intel_pxp_fini(&gt->pxp);



	/*

	 * Upon unregistering the device to prevent any new users, cancel

	 * all in-flight requests so that we can quickly unbind the active

drivers/gpu/drm/i915/gt/intel_gt_types.h

+3 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include "intel_rps_types.h"

#include "intel_migrate_types.h"

#include "intel_wakeref.h"

#include "pxp/intel_pxp_types.h"



struct drm_i915_private;

struct i915_ggtt;
@@ -201,6 +202,8 @@ struct intel_gt { 
	struct {

		u8 uc_index;

	} mocs;



	struct intel_pxp pxp;

};



enum intel_gt_scratch_field {

drivers/gpu/drm/i915/pxp/intel_pxp.c

0 → 100644
+70 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: MIT

/*

 * Copyright(c) 2020 Intel Corporation.

 */

#include "intel_pxp.h"

#include "gt/intel_context.h"

#include "i915_drv.h"



struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)

{

	return container_of(pxp, struct intel_gt, pxp);

}



static int create_vcs_context(struct intel_pxp *pxp)

{

	static struct lock_class_key pxp_lock;

	struct intel_gt *gt = pxp_to_gt(pxp);

	struct intel_engine_cs *engine;

	struct intel_context *ce;

	int i;



	/*

	 * Find the first VCS engine present. We're guaranteed there is one

	 * if we're in this function due to the check in has_pxp

	 */

	for (i = 0, engine = NULL; !engine; i++)

		engine = gt->engine_class[VIDEO_DECODE_CLASS][i];



	GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS);



	ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,

						I915_GEM_HWS_PXP_ADDR,

						&pxp_lock, "pxp_context");

	if (IS_ERR(ce)) {

		drm_err(&gt->i915->drm, "failed to create VCS ctx for PXP\n");

		return PTR_ERR(ce);

	}



	pxp->ce = ce;



	return 0;

}



static void destroy_vcs_context(struct intel_pxp *pxp)

{

	intel_engine_destroy_pinned_context(fetch_and_zero(&pxp->ce));

}



void intel_pxp_init(struct intel_pxp *pxp)

{

	struct intel_gt *gt = pxp_to_gt(pxp);

	int ret;



	if (!HAS_PXP(gt->i915))

		return;



	ret = create_vcs_context(pxp);

	if (ret)

		return;



	drm_info(&gt->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");

}



void intel_pxp_fini(struct intel_pxp *pxp)

{

	if (!intel_pxp_is_enabled(pxp))

		return;



	destroy_vcs_context(pxp);

}