Commit 3a9f66cb authored by Atish Patra's avatar Atish Patra Committed by Anup Patel
Browse files

RISC-V: KVM: Add timer functionality 



The RISC-V hypervisor specification doesn't have any virtual timer
feature.

Due to this, the guest VCPU timer will be programmed via SBI calls.
The host will use a separate hrtimer event for each guest VCPU to
provide timer functionality. We inject a virtual timer interrupt to
the guest VCPU whenever the guest VCPU hrtimer event expires.

This patch adds guest VCPU timer implementation along with ONE_REG
interface to access VCPU timer state from user space.

Signed-off-by: default avatarAtish Patra <atish.patra@wdc.com>
Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
Acked-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Reviewed-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Acked-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 9955371c

arch/riscv/include/asm/kvm_host.h

+7 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/types.h>

#include <linux/kvm.h>

#include <linux/kvm_types.h>

#include <asm/kvm_vcpu_timer.h>



#ifdef CONFIG_64BIT

#define KVM_MAX_VCPUS			(1U << 16)
@@ -60,6 +61,9 @@ struct kvm_arch { 
	/* stage2 page table */

	pgd_t *pgd;

	phys_addr_t pgd_phys;



	/* Guest Timer */

	struct kvm_guest_timer timer;

};



struct kvm_mmio_decode {
@@ -175,6 +179,9 @@ struct kvm_vcpu_arch { 
	unsigned long irqs_pending;

	unsigned long irqs_pending_mask;



	/* VCPU Timer */

	struct kvm_vcpu_timer timer;



	/* MMIO instruction details */

	struct kvm_mmio_decode mmio_decode;

arch/riscv/include/asm/kvm_vcpu_timer.h

0 → 100644
+44 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2019 Western Digital Corporation or its affiliates.

 *

 * Authors:

 *	Atish Patra <atish.patra@wdc.com>

 */



#ifndef __KVM_VCPU_RISCV_TIMER_H

#define __KVM_VCPU_RISCV_TIMER_H



#include <linux/hrtimer.h>



struct kvm_guest_timer {

	/* Mult & Shift values to get nanoseconds from cycles */

	u32 nsec_mult;

	u32 nsec_shift;

	/* Time delta value */

	u64 time_delta;

};



struct kvm_vcpu_timer {

	/* Flag for whether init is done */

	bool init_done;

	/* Flag for whether timer event is configured */

	bool next_set;

	/* Next timer event cycles */

	u64 next_cycles;

	/* Underlying hrtimer instance */

	struct hrtimer hrt;

};



int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles);

int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,

				 const struct kvm_one_reg *reg);

int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu,

				 const struct kvm_one_reg *reg);

int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu);

int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu);

int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu);

void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu);

int kvm_riscv_guest_timer_init(struct kvm *kvm);



#endif

arch/riscv/include/uapi/asm/kvm.h

+17 −0
Original line number Diff line number Diff line
@@ -74,6 +74,18 @@ struct kvm_riscv_csr { 
	unsigned long scounteren;

};



/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */

struct kvm_riscv_timer {

	__u64 frequency;

	__u64 time;

	__u64 compare;

	__u64 state;

};



/* Possible states for kvm_riscv_timer */

#define KVM_RISCV_TIMER_STATE_OFF	0

#define KVM_RISCV_TIMER_STATE_ON	1



#define KVM_REG_SIZE(id)		\

	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
@@ -96,6 +108,11 @@ struct kvm_riscv_csr { 
#define KVM_REG_RISCV_CSR_REG(name)	\

		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))



/* Timer registers are mapped as type 4 */

#define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)

#define KVM_REG_RISCV_TIMER_REG(name)	\

		(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))



#endif



#endif /* __LINUX_KVM_RISCV_H */

arch/riscv/kvm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -21,3 +21,4 @@ kvm-y += mmu.o 
kvm-y += vcpu.o

kvm-y += vcpu_exit.o

kvm-y += vcpu_switch.o

kvm-y += vcpu_timer.o

arch/riscv/kvm/vcpu.c

+14 −0
Original line number Diff line number Diff line
@@ -58,6 +58,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) 


	memcpy(cntx, reset_cntx, sizeof(*cntx));



	kvm_riscv_vcpu_timer_reset(vcpu);



	WRITE_ONCE(vcpu->arch.irqs_pending, 0);

	WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);

}
@@ -85,6 +87,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 
	cntx->hstatus |= HSTATUS_SPVP;

	cntx->hstatus |= HSTATUS_SPV;



	/* Setup VCPU timer */

	kvm_riscv_vcpu_timer_init(vcpu);



	/* Reset VCPU */

	kvm_riscv_reset_vcpu(vcpu);
@@ -97,6 +102,9 @@ void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 


void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)

{

	/* Cleanup VCPU timer */

	kvm_riscv_vcpu_timer_deinit(vcpu);



	/* Flush the pages pre-allocated for Stage2 page table mappings */

	kvm_riscv_stage2_flush_cache(vcpu);

}
@@ -332,6 +340,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, 
		return kvm_riscv_vcpu_set_reg_core(vcpu, reg);

	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)

		return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);

	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)

		return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);



	return -EINVAL;

}
@@ -345,6 +355,8 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, 
		return kvm_riscv_vcpu_get_reg_core(vcpu, reg);

	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)

		return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);

	else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)

		return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);



	return -EINVAL;

}
@@ -579,6 +591,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 


	kvm_riscv_stage2_update_hgatp(vcpu);



	kvm_riscv_vcpu_timer_restore(vcpu);



	vcpu->cpu = cpu;

}