ice: implement basic E822 PTP support

#define PF_SB_ATQT				0x0022FE00

#define PF_SB_ATQT_ATQT_S			0

#define PF_SB_ATQT_ATQT_M			ICE_M(0x3FF, 0)

#define PF_SB_REM_DEV_CTL			0x002300F0

#define PRTDCB_GENC				0x00083000

#define PRTDCB_GENC_PFCLDA_S			16

#define PRTDCB_GENC_PFCLDA_M			ICE_M(0xFFFF, 16)

	if (link_up == old_link && link_speed == old_link_speed)

		return 0;

	if (!ice_is_e810(&pf->hw))

		ice_ptp_link_change(pf, pf->hw.pf_id, link_up);

	if (ice_is_dcb_active(pf)) {

		if (test_bit(ICE_FLAG_DCB_ENA, pf->flags))

			ice_dcb_rebuild(pf);

		ice_print_link_msg(vsi, true);

		netif_tx_start_all_queues(vsi->netdev);

		netif_carrier_on(vsi->netdev);

		if (!ice_is_e810(&pf->hw))

			ice_ptp_link_change(pf, pf->hw.pf_id, true);

	}

	/* clear this now, and the first stats read will be used as baseline */

	WARN_ON(!test_bit(ICE_VSI_DOWN, vsi->state));

	if (vsi->netdev && vsi->type == ICE_VSI_PF) {

		if (!ice_is_e810(&vsi->back->hw))

			ice_ptp_link_change(vsi->back, vsi->back->hw.pf_id, false);

		netif_carrier_off(vsi->netdev);

		netif_tx_disable(vsi->netdev);

	} else if (vsi->type == ICE_VSI_SWITCHDEV_CTRL) {

#define E810_OUT_PROP_DELAY_NS 1

#define UNKNOWN_INCVAL_E822 0x100000000ULL

static const struct ptp_pin_desc ice_pin_desc_e810t[] = {

	/* name    idx   func         chan */

	{ "GNSS",  GNSS, PTP_PF_EXTTS, 0, { 0, } },

 */

static u64 ice_base_incval(struct ice_pf *pf)

{

	return ICE_PTP_NOMINAL_INCVAL_E810;

	struct ice_hw *hw = &pf->hw;

	u64 incval;

	if (ice_is_e810(hw))

		incval = ICE_PTP_NOMINAL_INCVAL_E810;

	else if (ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)

		incval = ice_e822_nominal_incval(ice_e822_time_ref(hw));

	else

		incval = UNKNOWN_INCVAL_E822;

	dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",

		incval);

	return incval;

}

/**

 * ice_ptp_reset_ts_memory_quad - Reset timestamp memory for one quad

 * @pf: The PF private data structure

 * @quad: The quad (0-4)

 */

static void ice_ptp_reset_ts_memory_quad(struct ice_pf *pf, int quad)

{

	struct ice_hw *hw = &pf->hw;

	ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);

	ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);

}

/**

 * ice_ptp_port_phy_stop - Stop timestamping for a PHY port

 * @ptp_port: PTP port to stop

 */

static int

ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)

{

	struct ice_pf *pf = ptp_port_to_pf(ptp_port);

	u8 port = ptp_port->port_num;

	struct ice_hw *hw = &pf->hw;

	int err;

	if (ice_is_e810(hw))

		return 0;

	mutex_lock(&ptp_port->ps_lock);

	err = ice_stop_phy_timer_e822(hw, port, true);

	if (err)

		dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",

			port, err);

	mutex_unlock(&ptp_port->ps_lock);

	return err;

}

/**

 * ice_ptp_port_phy_restart - (Re)start and calibrate PHY timestamping

 * @ptp_port: PTP port for which the PHY start is set

 *

 * Start the PHY timestamping block, and initiate Vernier timestamping

 * calibration. If timestamping cannot be calibrated (such as if link is down)

 * then disable the timestamping block instead.

 */

static int

ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)

{

	struct ice_pf *pf = ptp_port_to_pf(ptp_port);

	u8 port = ptp_port->port_num;

	struct ice_hw *hw = &pf->hw;

	int err;

	if (ice_is_e810(hw))

		return 0;

	if (!ptp_port->link_up)

		return ice_ptp_port_phy_stop(ptp_port);

	mutex_lock(&ptp_port->ps_lock);

	/* temporarily disable Tx timestamps while calibrating PHY offset */

	ptp_port->tx.calibrating = true;

	/* Start the PHY timer in bypass mode */

	err = ice_start_phy_timer_e822(hw, port, true);

	if (err)

		goto out_unlock;

	/* Enable Tx timestamps right away */

	ptp_port->tx.calibrating = false;

out_unlock:

	if (err)

		dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",

			port, err);

	mutex_unlock(&ptp_port->ps_lock);

	return err;

}

/**

 * ice_ptp_link_change - Set or clear port registers for timestamping

 * @pf: Board private structure

 * @port: Port for which the PHY start is set

 * @linkup: Link is up or down

 */

int ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)

{

	struct ice_ptp_port *ptp_port;

	if (!test_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags))

		return 0;

	if (port >= ICE_NUM_EXTERNAL_PORTS)

		return -EINVAL;

	ptp_port = &pf->ptp.port;

	if (ptp_port->port_num != port)

		return -EINVAL;

	/* Update cached link err for this port immediately */

	ptp_port->link_up = linkup;

	if (!test_bit(ICE_FLAG_PTP, pf->flags))

		/* PTP is not setup */

		return -EAGAIN;

	return ice_ptp_port_phy_restart(ptp_port);

}

/**

 * ice_ptp_reset_ts_memory - Reset timestamp memory for all quads

 * @pf: The PF private data structure

 */

static void ice_ptp_reset_ts_memory(struct ice_pf *pf)

{

	int quad;

	quad = pf->hw.port_info->lport / ICE_PORTS_PER_QUAD;

	ice_ptp_reset_ts_memory_quad(pf, quad);

}

/**

 * ice_ptp_tx_ena_intr - Enable or disable the Tx timestamp interrupt

 * @pf: PF private structure

 * @ena: bool value to enable or disable interrupt

 * @threshold: Minimum number of packets at which intr is triggered

 *

 * Utility function to enable or disable Tx timestamp interrupt and threshold

 */

static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold)

{

	struct ice_hw *hw = &pf->hw;

	int err = 0;

	int quad;

	u32 val;

	ice_ptp_reset_ts_memory(pf);

	for (quad = 0; quad < ICE_MAX_QUAD; quad++) {

		err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,

					     &val);

		if (err)

			break;

		if (ena) {

			val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;

			val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;

			val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) &

				Q_REG_TX_MEM_GBL_CFG_INTR_THR_M);

		} else {

			val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;

		}

		err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,

					      val);

		if (err)

			break;

	}

	if (err)

		dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",

			err);

	return err;

}

/**

 * ice_ptp_reset_phy_timestamping - Reset PHY timestamping block

 * @pf: Board private structure

 */

static void ice_ptp_reset_phy_timestamping(struct ice_pf *pf)

{

	ice_ptp_port_phy_restart(&pf->ptp.port);

}

/**

		start_time = div64_u64(current_time + NSEC_PER_SEC - 1,

				       NSEC_PER_SEC) * NSEC_PER_SEC + phase;

	if (ice_is_e810(hw))

		start_time -= E810_OUT_PROP_DELAY_NS;

	else

		start_time -= ice_e822_pps_delay(ice_e822_time_ref(hw));

	/* 2. Write TARGET time */

	wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));

	struct ice_hw *hw = &pf->hw;

	int err;

	/* For Vernier mode, we need to recalibrate after new settime

	 * Start with disabling timestamp block

	 */

	if (pf->ptp.port.link_up)

		ice_ptp_port_phy_stop(&pf->ptp.port);

	if (!ice_ptp_lock(hw)) {

		err = -EBUSY;

		goto exit;

	/* Reenable periodic outputs */

	ice_ptp_enable_all_clkout(pf);

	/* Recalibrate and re-enable timestamp block */

	if (pf->ptp.port.link_up)

		ice_ptp_port_phy_restart(&pf->ptp.port);

exit:

	if (err) {

		dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err);

	info->gettimex64 = ice_ptp_gettimex64;

	info->settime64 = ice_ptp_settime64;

	if (ice_is_e810(&pf->hw))

		ice_ptp_set_funcs_e810(pf, info);

}

	u8 idx;

	/* Check if this tracker is initialized */

	if (!tx->init)

	if (!tx->init || tx->calibrating)

		return -1;

	spin_lock(&tx->lock);

	tx->len = 0;

}

/**

 * ice_ptp_init_tx_e822 - Initialize tracking for Tx timestamps

 * @pf: Board private structure

 * @tx: the Tx tracking structure to initialize

 * @port: the port this structure tracks

 *

 * Initialize the Tx timestamp tracker for this port. For generic MAC devices,

 * the timestamp block is shared for all ports in the same quad. To avoid

 * ports using the same timestamp index, logically break the block of

 * registers into chunks based on the port number.

 */

static int

ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)

{

	tx->quad = port / ICE_PORTS_PER_QUAD;

	tx->quad_offset = tx->quad * INDEX_PER_PORT;

	tx->len = INDEX_PER_PORT;

	return ice_ptp_alloc_tx_tracker(tx);

}

/**

 * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps

 * @pf: Board private structure

	struct ice_ptp *ptp = &pf->ptp;

	struct ice_hw *hw = &pf->hw;

	struct timespec64 ts;

	int err, itr = 1;

	u64 time_diff;

	int err = 1;

	if (test_bit(ICE_PFR_REQ, pf->state))

		goto pfr;

	if (!hw->func_caps.ts_func_info.src_tmr_owned)

		goto pfr;

		goto reset_ts;

	err = ice_ptp_init_phc(hw);

	if (err)

	/* Release the global hardware lock */

	ice_ptp_unlock(hw);

	if (!ice_is_e810(hw)) {

		/* Enable quad interrupts */

		err = ice_ptp_tx_ena_intr(pf, true, itr);

		if (err)

			goto err;

	}

reset_ts:

	/* Restart the PHY timestamping block */

	ice_ptp_reset_phy_timestamping(pf);

pfr:

	/* Init Tx structures */

	if (ice_is_e810(&pf->hw))

		err = ice_ptp_init_tx_e810(pf, &ptp->port.tx);

	else

		err = ice_ptp_init_tx_e822(pf, &ptp->port.tx,

					   ptp->port.port_num);

	if (err)

		goto err;

{

	struct ice_hw *hw = &pf->hw;

	struct timespec64 ts;

	int err;

	int err, itr = 1;

	err = ice_ptp_init_phc(hw);

	if (err) {

	/* Release the global hardware lock */

	ice_ptp_unlock(hw);

	if (!ice_is_e810(hw)) {

		/* Enable quad interrupts */

		err = ice_ptp_tx_ena_intr(pf, true, itr);

		if (err)

			goto err_exit;

	}

	/* Ensure we have a clock device */

	err = ice_ptp_create_clock(pf);

	if (err)

	return 0;

}

/**

 * ice_ptp_init_port - Initialize PTP port structure

 * @pf: Board private structure

 * @ptp_port: PTP port structure

 */

static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)

{

	mutex_init(&ptp_port->ps_lock);

	if (ice_is_e810(&pf->hw))

		return ice_ptp_init_tx_e810(pf, &ptp_port->tx);

	return ice_ptp_init_tx_e822(pf, &ptp_port->tx, ptp_port->port_num);

}

/**

 * ice_ptp_init - Initialize PTP hardware clock support

 * @pf: Board private structure

	struct ice_hw *hw = &pf->hw;

	int err;

	/* PTP is currently only supported on E810 devices */

	if (!ice_is_e810(hw))

		return;

	/* If this function owns the clock hardware, it must allocate and

	 * configure the PTP clock device to represent it.

	 */

			goto err;

	}

	err = ice_ptp_init_tx_e810(pf, &pf->ptp.port.tx);

	ptp->port.port_num = hw->pf_id;

	err = ice_ptp_init_port(pf, &ptp->port);

	if (err)

		goto err;

	/* Start the PHY timestamping block */

	ice_ptp_reset_phy_timestamping(pf);

	set_bit(ICE_FLAG_PTP, pf->flags);

	err = ice_ptp_init_work(pf, ptp);

	if (err)

	kthread_cancel_delayed_work_sync(&pf->ptp.work);

	ice_ptp_port_phy_stop(&pf->ptp.port);

	mutex_destroy(&pf->ptp.port.ps_lock);

	if (pf->ptp.kworker) {

		kthread_destroy_worker(pf->ptp.kworker);

		pf->ptp.kworker = NULL;

 * @quad_offset: offset into timestamp block of the quad to get the real index

 * @len: length of the tstamps and in_use fields.

 * @init: if true, the tracker is initialized;

 * @calibrating: if true, the PHY is calibrating the Tx offset. During this

 *               window, timestamps are temporarily disabled.

 */

struct ice_ptp_tx {

	struct kthread_work work;

	u8 quad_offset;

	u8 len;

	u8 init;

	u8 calibrating;

};

/* Quad and port information for initializing timestamp blocks */

/**

 * struct ice_ptp_port - data used to initialize an external port for PTP

 *

 * This structure contains PTP data related to the external ports. Currently

 * it is used for tracking the Tx timestamps of a port. In the future this

 * structure will also hold information for the E822 port initialization

 * logic.

 * This structure contains data indicating whether a single external port is

 * ready for PTP functionality. It is used to track the port initialization

 * and determine when the port's PHY offset is valid.

 *

 * @tx: Tx timestamp tracking for this port

 * @ps_lock: mutex used to protect the overall PTP PHY start procedure

 * @link_up: indicates whether the link is up

 * @port_num: the port number this structure represents

 */

struct ice_ptp_port {

	struct ice_ptp_tx tx;

	struct mutex ps_lock; /* protects overall PTP PHY start procedure */

	bool link_up;

	u8 port_num;

};

#define GLTSYN_TGT_H_IDX_MAX		4

#define ptp_info_to_pf(i) \

	container_of(__ptp_info_to_ptp((i)), struct ice_pf, ptp)

#define PFTSYN_SEM_BYTES		4

#define PTP_SHARED_CLK_IDX_VALID	BIT(31)

#define TS_CMD_MASK			0xF

#define SYNC_EXEC_CMD			0x3

#define ICE_PTP_TS_VALID		BIT(0)

#define FIFO_EMPTY			BIT(2)

#define FIFO_OK				0xFF

#define ICE_PTP_FIFO_NUM_CHECKS		5

/* Per-channel register definitions */

#define GLTSYN_AUX_OUT(_chan, _idx)	(GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))

#define GLTSYN_AUX_IN(_chan, _idx)	(GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8))

#define N_PER_OUT_E810T			3

#define N_PER_OUT_E810T_NO_SMA		2

#define N_EXT_TS_E810_NO_SMA		2

#define ETH_GLTSYN_ENA(_i)		(0x03000348 + ((_i) * 4))

#if IS_ENABLED(CONFIG_PTP_1588_CLOCK)

struct ice_pf;

void ice_ptp_prepare_for_reset(struct ice_pf *pf);

void ice_ptp_init(struct ice_pf *pf);

void ice_ptp_release(struct ice_pf *pf);

int ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup);

#else /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */

static inline int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)

{

static inline void ice_ptp_prepare_for_reset(struct ice_pf *pf) { }

static inline void ice_ptp_init(struct ice_pf *pf) { }

static inline void ice_ptp_release(struct ice_pf *pf) { }

static inline int ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)

{ return 0; }

#endif /* IS_ENABLED(CONFIG_PTP_1588_CLOCK) */

#endif /* _ICE_PTP_H_ */

/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (C) 2018-2021, Intel Corporation. */

#ifndef _ICE_PTP_CONSTS_H_

#define _ICE_PTP_CONSTS_H_

/* Constant definitions related to the hardware clock used for PTP 1588

 * features and functionality.

 */

/* Constants defined for the PTP 1588 clock hardware. */

/* struct ice_time_ref_info_e822

 *

 * E822 hardware can use different sources as the reference for the PTP

 * hardware clock. Each clock has different characteristics such as a slightly

 * different frequency, etc.

 *

 * This lookup table defines several constants that depend on the current time

 * reference. See the struct ice_time_ref_info_e822 for information about the

 * meaning of each constant.

 */

const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {

	/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */

	{

		/* pll_freq */

		823437500, /* 823.4375 MHz PLL */

		/* nominal_incval */

		0x136e44fabULL,

		/* pps_delay */

		11,

	},

	/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */

	{

		/* pll_freq */

		783360000, /* 783.36 MHz */

		/* nominal_incval */

		0x146cc2177ULL,

		/* pps_delay */

		12,

	},

	/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */

	{

		/* pll_freq */

		796875000, /* 796.875 MHz */

		/* nominal_incval */

		0x141414141ULL,

		/* pps_delay */

		12,

	},

	/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */

	{

		/* pll_freq */

		816000000, /* 816 MHz */

		/* nominal_incval */

		0x139b9b9baULL,

		/* pps_delay */

		12,

	},

	/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */

	{

		/* pll_freq */

		830078125, /* 830.78125 MHz */

		/* nominal_incval */

		0x134679aceULL,

		/* pps_delay */

		11,

	},

	/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */

	{

		/* pll_freq */

		783360000, /* 783.36 MHz */

		/* nominal_incval */

		0x146cc2177ULL,

		/* pps_delay */

		12,

	},

};

/* struct ice_vernier_info_e822

 *

 * E822 hardware calibrates the delay of the timestamp indication from the

 * actual packet transmission or reception during the initialization of the

 * PHY. To do this, the hardware mechanism uses some conversions between the

 * various clocks within the PHY block. This table defines constants used to

 * calculate the correct conversion ratios in the PHY registers.

 *

 * Many of the values relate to the PAR/PCS clock conversion registers. For

 * these registers, a value of 0 means that the associated register is not

 * used by this link speed, and that the register should be cleared by writing

 * 0. Other values specify the clock frequency in Hz.

 */

const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = {

	/* ICE_PTP_LNK_SPD_1G */

	{

		/* tx_par_clk */

		31250000, /* 31.25 MHz */

		/* rx_par_clk */

		31250000, /* 31.25 MHz */

		/* tx_pcs_clk */

		125000000, /* 125 MHz */

		/* rx_pcs_clk */

		125000000, /* 125 MHz */

		/* tx_desk_rsgb_par */

		0, /* unused */

		/* rx_desk_rsgb_par */

		0, /* unused */

		/* tx_desk_rsgb_pcs */

		0, /* unused */

		/* rx_desk_rsgb_pcs */

		0, /* unused */

		/* tx_fixed_delay */

		25140,

		/* pmd_adj_divisor */

		10000000,

		/* rx_fixed_delay */

		17372,

	},

	/* ICE_PTP_LNK_SPD_10G */

	{

		/* tx_par_clk */

		257812500, /* 257.8125 MHz */

		/* rx_par_clk */

		257812500, /* 257.8125 MHz */

		/* tx_pcs_clk */

		156250000, /* 156.25 MHz */

		/* rx_pcs_clk */

		156250000, /* 156.25 MHz */

		/* tx_desk_rsgb_par */

		0, /* unused */

		/* rx_desk_rsgb_par */

		0, /* unused */

		/* tx_desk_rsgb_pcs */

		0, /* unused */

		/* rx_desk_rsgb_pcs */

		0, /* unused */

		/* tx_fixed_delay */

		6938,

		/* pmd_adj_divisor */

		82500000,

		/* rx_fixed_delay */

		6212,

	},

	/* ICE_PTP_LNK_SPD_25G */

	{

		/* tx_par_clk */

		644531250, /* 644.53125 MHZ */

		/* rx_par_clk */

		644531250, /* 644.53125 MHz */

		/* tx_pcs_clk */

		390625000, /* 390.625 MHz */

		/* rx_pcs_clk */

		390625000, /* 390.625 MHz */

		/* tx_desk_rsgb_par */

		0, /* unused */

		/* rx_desk_rsgb_par */

		0, /* unused */

		/* tx_desk_rsgb_pcs */

		0, /* unused */

		/* rx_desk_rsgb_pcs */

		0, /* unused */

		/* tx_fixed_delay */

		2778,

		/* pmd_adj_divisor */

		206250000,

		/* rx_fixed_delay */

		2491,

	},

	/* ICE_PTP_LNK_SPD_25G_RS */

	{

		/* tx_par_clk */

		0, /* unused */

		/* rx_par_clk */

		0, /* unused */

		/* tx_pcs_clk */

		0, /* unused */

		/* rx_pcs_clk */

		0, /* unused */

		/* tx_desk_rsgb_par */

		161132812, /* 162.1328125 MHz Reed Solomon gearbox */

		/* rx_desk_rsgb_par */

		161132812, /* 162.1328125 MHz Reed Solomon gearbox */

		/* tx_desk_rsgb_pcs */

		97656250, /* 97.62625 MHz Reed Solomon gearbox */

		/* rx_desk_rsgb_pcs */

		97656250, /* 97.62625 MHz Reed Solomon gearbox */

		/* tx_fixed_delay */

		3928,

		/* pmd_adj_divisor */

		206250000,

		/* rx_fixed_delay */