Commit 3a57530b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung'... 

Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' and 'clk-allwinner' into clk-next

 - Allow the COMMON_CLK config to be selectable

* clk-selectable:
  clk: Move HAVE_CLK config out of architecture layer
  MIPS: Loongson64: Drop asm/clock.h include
  ARM: mmp: Remove legacy clk code
  clk: Allow the common clk framework to be selectable
  mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF
  MIPS: Remove redundant CLKDEV_LOOKUP selects
  h8300: Remove redundant CLKDEV_LOOKUP selects
  arm64: tegra: Remove redundant CLKDEV_LOOKUP selects
  ARM: Remove redundant CLKDEV_LOOKUP selects
  ARM: Remove redundant COMMON_CLK selects

* clk-amlogic:
  clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
  clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
  clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
  clk: meson: meson8b: Fix the polarity of the RESET_N lines
  clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
  clk: meson: g12a: Prepare the GPU clock tree to change at runtime
  clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
  clk: meson: meson8b: make the hdmi_sys clock tree mutable
  clk: meson8b: export the HDMI system clock

* clk-renesas:
  dt-bindings: clock: renesas: mstp: Convert to json-schema
  dt-bindings: clock: renesas: div6: Convert to json-schema
  clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
  clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
  clk: renesas: cpg-mssr: Add R8A7742 support
  dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
  clk: renesas: Add r8a7742 CPG Core Clock Definitions
  dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
  MAINTAINERS: Add DT Bindings for Renesas Clock Generators
  clk: renesas: r9a06g032: Fix some typo in comments
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support

* clk-samsung:
  clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
  ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
  clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
  clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical

* clk-allwinner:
  clk: sunxi: Fix incorrect usage of round_down()
parents bc8c945e 07fbf0e5 571a6b47 fe95d2e9 33b52f7c

Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas CPG DIV6 Clock



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description:

  The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse

  Generator (CPG). Their clock input is divided by a configurable factor from 1

  to 64.



properties:

  compatible:

    items:

      - enum:

          - renesas,r8a73a4-div6-clock # R-Mobile APE6

          - renesas,r8a7740-div6-clock # R-Mobile A1

          - renesas,sh73a0-div6-clock  # SH-Mobile AG5

      - const: renesas,cpg-div6-clock



  reg:

    maxItems: 1



  clocks:

    oneOf:

      - maxItems: 1

      - maxItems: 4

      - maxItems: 8

    description:

      For clocks with multiple parents, invalid settings must be specified as

      "<0>".



  '#clock-cells':

    const: 0



  clock-output-names: true



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a73a4-clock.h>

    sdhi2_clk: sdhi2_clk@e615007c {

            compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

            reg = <0xe615007c 4>;

            clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,

                     <&extal2_clk>;

            #clock-cells = <0>;

    };

Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt

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* Renesas CPG DIV6 Clock



The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse

Generator (CPG). Their clock input is divided by a configurable factor from 1

to 64.



Required Properties:



  - compatible: Must be one of the following

    - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks

    - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks

    - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks

    - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks

    - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks

    - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks

    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks

    and "renesas,cpg-div6-clock" as a fallback.

  - reg: Base address and length of the memory resource used by the DIV6 clock

  - clocks: Reference to the parent clock(s); either one, four, or eight

    clocks must be specified.  For clocks with multiple parents, invalid

    settings must be specified as "<0>".

  - #clock-cells: Must be 0





Optional Properties:



  - clock-output-names: The name of the clock as a free-form string





Example

-------



	sdhi2_clk: sdhi2_clk@e615007c {

		compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

		reg = <0 0xe615007c 0 4>;

		clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

			 <0>, <&extal2_clk>;

		#clock-cells = <0>;

		clock-output-names = "sdhi2ck";

	};

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

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@@ -25,6 +25,7 @@ properties: 
  compatible:

    enum:

      - renesas,r7s9210-cpg-mssr  # RZ/A2

      - renesas,r8a7742-cpg-mssr  # RZ/G1H

      - renesas,r8a7743-cpg-mssr  # RZ/G1M

      - renesas,r8a7744-cpg-mssr  # RZ/G1N

      - renesas,r8a7745-cpg-mssr  # RZ/G1E

Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt

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* Renesas CPG Module Stop (MSTP) Clocks



The CPG can gate SoC device clocks. The gates are organized in groups of up to

32 gates.



This device tree binding describes a single 32 gate clocks group per node.

Clocks are referenced by user nodes by the MSTP node phandle and the clock

index in the group, from 0 to 31.



Required Properties:



  - compatible: Must be one of the following

    - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks

    - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks

    - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks

    - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks

    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks

    - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks

    - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks

    - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks

    - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks

    - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks

    - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks

    and "renesas,cpg-mstp-clocks" as a fallback.

  - reg: Base address and length of the I/O mapped registers used by the MSTP

    clocks. The first register is the clock control register and is mandatory.

    The second register is the clock status register and is optional when not

    implemented in hardware.

  - clocks: Reference to the parent clocks, one per output clock. The parents

    must appear in the same order as the output clocks.

  - #clock-cells: Must be 1

  - clock-output-names: The name of the clocks as free-form strings

  - clock-indices: Indices of the gate clocks into the group (0 to 31)



The clocks, clock-output-names and clock-indices properties contain one entry

per gate clock. The MSTP groups are sparsely populated. Unimplemented gate

clocks must not be declared.





Example

-------



	#include <dt-bindings/clock/r8a7790-clock.h>



	mstp3_clks: mstp3_clks@e615013c {

		compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

		reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;

		clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,

			 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,

			 <&mmc0_clk>;

		#clock-cells = <1>;

		clock-output-names =

			"tpu0", "mmcif1", "sdhi3", "sdhi2",

			 "sdhi1", "sdhi0", "mmcif0";

		clock-indices = <

			R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3

			R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0

			R8A7790_CLK_MMCIF0

		>;

	};

Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description:

  The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are

  organized in groups of up to 32 gates.



  This device tree binding describes a single 32 gate clocks group per node.

  Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle

  and the clock index in the group, from 0 to 31.



properties:

  compatible:

    items:

      - enum:

          - renesas,r7s72100-mstp-clocks # RZ/A1

          - renesas,r8a73a4-mstp-clocks  # R-Mobile APE6

          - renesas,r8a7740-mstp-clocks  # R-Mobile A1

          - renesas,r8a7778-mstp-clocks  # R-Car M1

          - renesas,r8a7779-mstp-clocks  # R-Car H1

          - renesas,sh73a0-mstp-clocks   # SH-Mobile AG5

      - const: renesas,cpg-mstp-clocks



  reg:

    minItems: 1

    items:

      - description: Module Stop Control Register (MSTPCR)

      - description: Module Stop Status Register (MSTPSR)



  clocks:

    minItems: 1

    maxItems: 32



  '#clock-cells':

    const: 1



  clock-indices:

    minItems: 1

    maxItems: 32



  clock-output-names:

    minItems: 1

    maxItems: 32



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - clock-indices

  - clock-output-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a73a4-clock.h>

    mstp2_clks: mstp2_clks@e6150138 {

            compatible = "renesas,r8a73a4-mstp-clocks",

                         "renesas,cpg-mstp-clocks";

            reg = <0xe6150138 4>, <0xe6150040 4>;

            clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,

                     <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;

            #clock-cells = <1>;

            clock-indices = <

                    R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1

                    R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1

                    R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3

                    R8A73A4_CLK_DMAC

            >;

            clock-output-names =

                    "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",

                    "dmac";

    };