Unverified Commit 3a4bf922 authored by Jon Lin's avatar Jon Lin Committed by Mark Brown
Browse files

spi: rockchip: Preset cs-high and clk polarity in setup progress 



After power up, the cs and clock is in default status, and the cs-high
and clock polarity dts property configuration will take no effect until
the calling of rockchip_spi_config in the first transmission.
So preset them to make sure a correct voltage before the first
transmission coming.

Signed-off-by: default avatarJon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20220216014028.8123-5-jon.lin@rock-chips.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 869f2c94

drivers/spi/spi-rockchip.c

+24 −0
Original line number Diff line number Diff line
@@ -713,6 +713,29 @@ static bool rockchip_spi_can_dma(struct spi_controller *ctlr, 
	return xfer->len / bytes_per_word >= rs->fifo_len;

}



static int rockchip_spi_setup(struct spi_device *spi)

{

	struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);

	u32 cr0;



	pm_runtime_get_sync(rs->dev);



	cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);



	cr0 &= ~(0x3 << CR0_SCPH_OFFSET);

	cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);

	if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)

		cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;

	else if (spi->chip_select <= 1)

		cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET);



	writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);



	pm_runtime_put(rs->dev);



	return 0;

}



static int rockchip_spi_probe(struct platform_device *pdev)

{

	int ret;
@@ -840,6 +863,7 @@ static int rockchip_spi_probe(struct platform_device *pdev) 
	ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;

	ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);



	ctlr->setup = rockchip_spi_setup;

	ctlr->set_cs = rockchip_spi_set_cs;

	ctlr->transfer_one = rockchip_spi_transfer_one;

	ctlr->max_transfer_size = rockchip_spi_max_transfer_size;